Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux
authorLinus Torvalds <torvalds@linux-foundation.org>
Fri, 14 Oct 2022 19:38:03 +0000 (12:38 -0700)
committerLinus Torvalds <torvalds@linux-foundation.org>
Fri, 14 Oct 2022 19:38:03 +0000 (12:38 -0700)
Pull arm64 fixes from Catalin Marinas:

 - Cortex-A55 errata workaround (repeat TLBI)

 - AMPERE1 added to the Spectre-BHB affected list

 - MTE fix to avoid setting PG_mte_tagged if no tags have been touched
   on a page

 - Fixed typo in the SCTLR_EL1.SPINTMASK bit naming (the commit log has
   other typos)

 - perf: return value check in ali_drw_pmu_probe(),
   ALIBABA_UNCORE_DRW_PMU dependency on ACPI

* tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux:
  arm64: Add AMPERE1 to the Spectre-BHB affected list
  arm64: mte: Avoid setting PG_mte_tagged if no tags cleared or restored
  MAINTAINERS: rectify file entry in ALIBABA PMU DRIVER
  drivers/perf: ALIBABA_UNCORE_DRW_PMU should depend on ACPI
  drivers/perf: fix return value check in ali_drw_pmu_probe()
  arm64: errata: Add Cortex-A55 to the repeat tlbi list
  arm64/sysreg: Fix typo in SCTR_EL1.SPINTMASK

Documentation/arm64/silicon-errata.rst
MAINTAINERS
arch/arm64/Kconfig
arch/arm64/include/asm/cputype.h
arch/arm64/kernel/cpu_errata.c
arch/arm64/kernel/mte.c
arch/arm64/kernel/proton-pack.c
arch/arm64/mm/mteswap.c
arch/arm64/tools/sysreg
drivers/perf/Kconfig
drivers/perf/alibaba_uncore_drw_pmu.c

index 17d9fc5d14fbb6ca93a4069253dee15835fe9a59..808ade4cc008ac7c41b0a13e5685fe5afae1dfe3 100644 (file)
@@ -76,6 +76,8 @@ stable kernels.
 +----------------+-----------------+-----------------+-----------------------------+
 | ARM            | Cortex-A55      | #1530923        | ARM64_ERRATUM_1530923       |
 +----------------+-----------------+-----------------+-----------------------------+
+| ARM            | Cortex-A55      | #2441007        | ARM64_ERRATUM_2441007       |
++----------------+-----------------+-----------------+-----------------------------+
 | ARM            | Cortex-A57      | #832075         | ARM64_ERRATUM_832075        |
 +----------------+-----------------+-----------------+-----------------------------+
 | ARM            | Cortex-A57      | #852523         | N/A                         |
index f9654544ae2918f097655b2fae608d04d357ec93..72e80c0f6d55b8ea540011f883a7e260fefff00e 100644 (file)
@@ -752,7 +752,7 @@ ALIBABA PMU DRIVER
 M:     Shuai Xue <xueshuai@linux.alibaba.com>
 S:     Supported
 F:     Documentation/admin-guide/perf/alibaba_pmu.rst
-F:     drivers/perf/alibaba_uncore_dwr_pmu.c
+F:     drivers/perf/alibaba_uncore_drw_pmu.c
 
 ALIENWARE WMI DRIVER
 L:     Dell.Client.Kernel@dell.com
index f6737d2f37b2fe96e5896f36c8e508d7130cf76a..505c8a1ccbe0cd043d672a8e1192e052ac73d84a 100644 (file)
@@ -632,6 +632,23 @@ config ARM64_ERRATUM_1530923
 config ARM64_WORKAROUND_REPEAT_TLBI
        bool
 
+config ARM64_ERRATUM_2441007
+       bool "Cortex-A55: Completion of affected memory accesses might not be guaranteed by completion of a TLBI"
+       default y
+       select ARM64_WORKAROUND_REPEAT_TLBI
+       help
+         This option adds a workaround for ARM Cortex-A55 erratum #2441007.
+
+         Under very rare circumstances, affected Cortex-A55 CPUs
+         may not handle a race between a break-before-make sequence on one
+         CPU, and another CPU accessing the same page. This could allow a
+         store to a page that has been unmapped.
+
+         Work around this by adding the affected CPUs to the list that needs
+         TLB sequences to be done twice.
+
+         If unsure, say Y.
+
 config ARM64_ERRATUM_1286807
        bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation"
        default y
index 8aa0d276a63628f51d1d533c0f7a9e41fc9bfdb0..abc418650fec04fda7f79c2c46f3ec255124781d 100644 (file)
@@ -60,6 +60,7 @@
 #define ARM_CPU_IMP_FUJITSU            0x46
 #define ARM_CPU_IMP_HISI               0x48
 #define ARM_CPU_IMP_APPLE              0x61
+#define ARM_CPU_IMP_AMPERE             0xC0
 
 #define ARM_CPU_PART_AEM_V8            0xD0F
 #define ARM_CPU_PART_FOUNDATION                0xD00
 #define APPLE_CPU_PART_M1_ICESTORM_MAX 0x028
 #define APPLE_CPU_PART_M1_FIRESTORM_MAX        0x029
 
+#define AMPERE_CPU_PART_AMPERE1                0xAC3
+
 #define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)
 #define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)
 #define MIDR_CORTEX_A72 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72)
 #define MIDR_APPLE_M1_FIRESTORM_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM_PRO)
 #define MIDR_APPLE_M1_ICESTORM_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM_MAX)
 #define MIDR_APPLE_M1_FIRESTORM_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM_MAX)
+#define MIDR_AMPERE1 MIDR_CPU_MODEL(ARM_CPU_IMP_AMPERE, AMPERE_CPU_PART_AMPERE1)
 
 /* Fujitsu Erratum 010001 affects A64FX 1.0 and 1.1, (v0r0 and v1r0) */
 #define MIDR_FUJITSU_ERRATUM_010001            MIDR_FUJITSU_A64FX
index 58ca4f6b25d6a89375fa7588e95a9e6106d1e453..89ac00084f38a4584924bd2da8e2e0e9c5341a07 100644 (file)
@@ -230,6 +230,11 @@ static const struct arm64_cpu_capabilities arm64_repeat_tlbi_list[] = {
                ERRATA_MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xe),
        },
 #endif
+#ifdef CONFIG_ARM64_ERRATUM_2441007
+       {
+               ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
+       },
+#endif
 #ifdef CONFIG_ARM64_ERRATUM_2441009
        {
                /* Cortex-A510 r0p0 -> r1p1. Fixed in r1p2 */
index aca88470fb69d5dca875d7c4b73591997fc64ff7..7467217c1eaf372d19a0eed8398e2e89e04f44c7 100644 (file)
@@ -48,7 +48,12 @@ static void mte_sync_page_tags(struct page *page, pte_t old_pte,
        if (!pte_is_tagged)
                return;
 
-       mte_clear_page_tags(page_address(page));
+       /*
+        * Test PG_mte_tagged again in case it was racing with another
+        * set_pte_at().
+        */
+       if (!test_and_set_bit(PG_mte_tagged, &page->flags))
+               mte_clear_page_tags(page_address(page));
 }
 
 void mte_sync_tags(pte_t old_pte, pte_t pte)
@@ -64,7 +69,7 @@ void mte_sync_tags(pte_t old_pte, pte_t pte)
 
        /* if PG_mte_tagged is set, tags have already been initialised */
        for (i = 0; i < nr_pages; i++, page++) {
-               if (!test_and_set_bit(PG_mte_tagged, &page->flags))
+               if (!test_bit(PG_mte_tagged, &page->flags))
                        mte_sync_page_tags(page, old_pte, check_swap,
                                           pte_is_tagged);
        }
index a8ea1637b13798ce49a594d79f410efd4e49703e..bfce41c2a53b3a396f7231ef359946aca0027de9 100644 (file)
@@ -868,6 +868,10 @@ u8 spectre_bhb_loop_affected(int scope)
                        MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1),
                        {},
                };
+               static const struct midr_range spectre_bhb_k11_list[] = {
+                       MIDR_ALL_VERSIONS(MIDR_AMPERE1),
+                       {},
+               };
                static const struct midr_range spectre_bhb_k8_list[] = {
                        MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
                        MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
@@ -878,6 +882,8 @@ u8 spectre_bhb_loop_affected(int scope)
                        k = 32;
                else if (is_midr_in_range_list(read_cpuid_id(), spectre_bhb_k24_list))
                        k = 24;
+               else if (is_midr_in_range_list(read_cpuid_id(), spectre_bhb_k11_list))
+                       k = 11;
                else if (is_midr_in_range_list(read_cpuid_id(), spectre_bhb_k8_list))
                        k =  8;
 
index 4334dec93bd441eb285d27b97d2b86cfdf1d00c0..bed803d8e15856b56468fcbc6b271f82b4466261 100644 (file)
@@ -53,7 +53,12 @@ bool mte_restore_tags(swp_entry_t entry, struct page *page)
        if (!tags)
                return false;
 
-       mte_restore_page_tags(page_address(page), tags);
+       /*
+        * Test PG_mte_tagged again in case it was racing with another
+        * set_pte_at().
+        */
+       if (!test_and_set_bit(PG_mte_tagged, &page->flags))
+               mte_restore_page_tags(page_address(page), tags);
 
        return true;
 }
index 7f1fb36f208ca4b2ac87203f536b80edac38cb91..384757a7eda9e3749c00610bde4fe022a7c944ea 100644 (file)
@@ -732,7 +732,7 @@ EndSysreg
 
 Sysreg SCTLR_EL1       3       0       1       0       0
 Field  63      TIDCP
-Field  62      SPINMASK
+Field  62      SPINTMASK
 Field  61      NMI
 Field  60      EnTP2
 Res0   59:58
index 44c07ea487f4482a5f95341329c99b2996bb4445..341010f20b777905f67d25dbb072fe4c515b487f 100644 (file)
@@ -185,7 +185,7 @@ config APPLE_M1_CPU_PMU
 
 config ALIBABA_UNCORE_DRW_PMU
        tristate "Alibaba T-Head Yitian 710 DDR Sub-system Driveway PMU driver"
-       depends on ARM64 || COMPILE_TEST
+       depends on (ARM64 && ACPI) || COMPILE_TEST
        help
          Support for Driveway PMU events monitoring on Yitian 710 DDR
          Sub-system.
index 82729b874f093ca18e7d3c63b84eeec9b6d18ca4..a7689fecb49d9611eb2b6f335f1212180e638660 100644 (file)
@@ -658,8 +658,8 @@ static int ali_drw_pmu_probe(struct platform_device *pdev)
 
        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
        drw_pmu->cfg_base = devm_ioremap_resource(&pdev->dev, res);
-       if (!drw_pmu->cfg_base)
-               return -ENOMEM;
+       if (IS_ERR(drw_pmu->cfg_base))
+               return PTR_ERR(drw_pmu->cfg_base);
 
        name = devm_kasprintf(drw_pmu->dev, GFP_KERNEL, "ali_drw_%llx",
                              (u64) (res->start >> ALI_DRW_PMU_PA_SHIFT));