drm/amdgpu: Use the right function for hdp flush
authorLijo Lazar <lijo.lazar@amd.com>
Fri, 11 Apr 2025 12:10:26 +0000 (17:40 +0530)
committerAlex Deucher <alexander.deucher@amd.com>
Fri, 11 Apr 2025 21:01:06 +0000 (17:01 -0400)
There are a few prechecks made before HDP flush like a flush is not
required on APU bare metal. Using hdp callback directly bypasses those
checks. Use amdgpu_device_flush_hdp which takes care of prechecks.

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
drivers/gpu/drm/amd/amdgpu/psp_v14_0.c

index f5dcb72a6bf5b73b09f1db9db53fff6e6034fe87..00eb4cfecf8f4f622de165aeb265fea5f32d4d09 100644 (file)
@@ -6172,7 +6172,7 @@ static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev)
        }
 
        if (amdgpu_emu_mode == 1)
-               adev->hdp.funcs->flush_hdp(adev, NULL);
+               amdgpu_device_flush_hdp(adev, NULL);
 
        tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL);
        tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
@@ -6250,7 +6250,7 @@ static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev)
        }
 
        if (amdgpu_emu_mode == 1)
-               adev->hdp.funcs->flush_hdp(adev, NULL);
+               amdgpu_device_flush_hdp(adev, NULL);
 
        tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL);
        tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0);
@@ -6327,7 +6327,7 @@ static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev)
        }
 
        if (amdgpu_emu_mode == 1)
-               adev->hdp.funcs->flush_hdp(adev, NULL);
+               amdgpu_device_flush_hdp(adev, NULL);
 
        tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL);
        tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
@@ -6702,7 +6702,7 @@ static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev)
        }
 
        if (amdgpu_emu_mode == 1)
-               adev->hdp.funcs->flush_hdp(adev, NULL);
+               amdgpu_device_flush_hdp(adev, NULL);
 
        tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL);
        tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
index 06ad10d06ca1c919c119669bfa11602bfc321138..ac90f823e596c9568175a2fb10045d056f9d1b2b 100644 (file)
@@ -2509,7 +2509,7 @@ static int gfx_v11_0_config_me_cache(struct amdgpu_device *adev, uint64_t addr)
        }
 
        if (amdgpu_emu_mode == 1)
-               adev->hdp.funcs->flush_hdp(adev, NULL);
+               amdgpu_device_flush_hdp(adev, NULL);
 
        tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL);
        tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
@@ -2553,7 +2553,7 @@ static int gfx_v11_0_config_pfp_cache(struct amdgpu_device *adev, uint64_t addr)
        }
 
        if (amdgpu_emu_mode == 1)
-               adev->hdp.funcs->flush_hdp(adev, NULL);
+               amdgpu_device_flush_hdp(adev, NULL);
 
        tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL);
        tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
@@ -2598,7 +2598,7 @@ static int gfx_v11_0_config_mec_cache(struct amdgpu_device *adev, uint64_t addr)
        }
 
        if (amdgpu_emu_mode == 1)
-               adev->hdp.funcs->flush_hdp(adev, NULL);
+               amdgpu_device_flush_hdp(adev, NULL);
 
        tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL);
        tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
@@ -3234,7 +3234,7 @@ static int gfx_v11_0_cp_gfx_load_pfp_microcode_rs64(struct amdgpu_device *adev)
        amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_data_obj);
 
        if (amdgpu_emu_mode == 1)
-               adev->hdp.funcs->flush_hdp(adev, NULL);
+               amdgpu_device_flush_hdp(adev, NULL);
 
        WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO,
                lower_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));
@@ -3452,7 +3452,7 @@ static int gfx_v11_0_cp_gfx_load_me_microcode_rs64(struct amdgpu_device *adev)
        amdgpu_bo_unreserve(adev->gfx.me.me_fw_data_obj);
 
        if (amdgpu_emu_mode == 1)
-               adev->hdp.funcs->flush_hdp(adev, NULL);
+               amdgpu_device_flush_hdp(adev, NULL);
 
        WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO,
                lower_32_bits(adev->gfx.me.me_fw_gpu_addr));
@@ -4648,7 +4648,7 @@ static int gfx_v11_0_gfxhub_enable(struct amdgpu_device *adev)
        if (r)
                return r;
 
-       adev->hdp.funcs->flush_hdp(adev, NULL);
+       amdgpu_device_flush_hdp(adev, NULL);
 
        value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ?
                false : true;
index 2474006b1a3407c1d23c5566dd91c1cc25a9dbd7..f347921fa9097403c0d22473e36d5e484ad6c49f 100644 (file)
@@ -2389,7 +2389,7 @@ static int gfx_v12_0_cp_gfx_load_pfp_microcode_rs64(struct amdgpu_device *adev)
        amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_data_obj);
 
        if (amdgpu_emu_mode == 1)
-               adev->hdp.funcs->flush_hdp(adev, NULL);
+               amdgpu_device_flush_hdp(adev, NULL);
 
        WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO,
                lower_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));
@@ -2533,7 +2533,7 @@ static int gfx_v12_0_cp_gfx_load_me_microcode_rs64(struct amdgpu_device *adev)
        amdgpu_bo_unreserve(adev->gfx.me.me_fw_data_obj);
 
        if (amdgpu_emu_mode == 1)
-               adev->hdp.funcs->flush_hdp(adev, NULL);
+               amdgpu_device_flush_hdp(adev, NULL);
 
        WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO,
                lower_32_bits(adev->gfx.me.me_fw_gpu_addr));
@@ -3503,7 +3503,7 @@ static int gfx_v12_0_gfxhub_enable(struct amdgpu_device *adev)
        if (r)
                return r;
 
-       adev->hdp.funcs->flush_hdp(adev, NULL);
+       amdgpu_device_flush_hdp(adev, NULL);
 
        value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ?
                false : true;
index b6ac4c7adc8a65922c80c90f03d8007d8d2be7e7..7648e977b44bc3567c9b92a6b39d134be7e87d35 100644 (file)
@@ -268,7 +268,7 @@ static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
        ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng;
 
        /* flush hdp cache */
-       adev->hdp.funcs->flush_hdp(adev, NULL);
+       amdgpu_device_flush_hdp(adev, NULL);
 
        /* This is necessary for SRIOV as well as for GFXOFF to function
         * properly under bare metal
@@ -965,7 +965,7 @@ static int gmc_v10_0_gart_enable(struct amdgpu_device *adev)
        adev->hdp.funcs->init_registers(adev);
 
        /* Flush HDP after it is initialized */
-       adev->hdp.funcs->flush_hdp(adev, NULL);
+       amdgpu_device_flush_hdp(adev, NULL);
 
        value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ?
                false : true;
index 5c91d4445418cfb0e6f60ca87950cea72c44593b..7f5ca170f141adf8516aaaeb6706df08ff4feb2e 100644 (file)
@@ -229,7 +229,7 @@ static void gmc_v11_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
        ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng;
 
        /* flush hdp cache */
-       adev->hdp.funcs->flush_hdp(adev, NULL);
+       amdgpu_device_flush_hdp(adev, NULL);
 
        /* This is necessary for SRIOV as well as for GFXOFF to function
         * properly under bare metal
@@ -895,7 +895,7 @@ static int gmc_v11_0_gart_enable(struct amdgpu_device *adev)
                return r;
 
        /* Flush HDP after it is initialized */
-       adev->hdp.funcs->flush_hdp(adev, NULL);
+       amdgpu_device_flush_hdp(adev, NULL);
 
        value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ?
                false : true;
index d544419e3b44a0795871d0f6a789614e7bef4425..b645d3e6a6c81acab011e7136a54239693d156d9 100644 (file)
@@ -297,7 +297,7 @@ static void gmc_v12_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
                return;
 
        /* flush hdp cache */
-       adev->hdp.funcs->flush_hdp(adev, NULL);
+       amdgpu_device_flush_hdp(adev, NULL);
 
        /* This is necessary for SRIOV as well as for GFXOFF to function
         * properly under bare metal
@@ -877,7 +877,7 @@ static int gmc_v12_0_gart_enable(struct amdgpu_device *adev)
                return r;
 
        /* Flush HDP after it is initialized */
-       adev->hdp.funcs->flush_hdp(adev, NULL);
+       amdgpu_device_flush_hdp(adev, NULL);
 
        value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ?
                false : true;
index 8d3560314e5b2e107814ed7488105e1c0e72d930..53050176c244daeb5c0623b9de1318461434dcc3 100644 (file)
@@ -2425,7 +2425,7 @@ static int gmc_v9_0_hw_init(struct amdgpu_ip_block *ip_block)
        adev->hdp.funcs->init_registers(adev);
 
        /* After HDP is initialized, flush HDP.*/
-       adev->hdp.funcs->flush_hdp(adev, NULL);
+       amdgpu_device_flush_hdp(adev, NULL);
 
        if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
                value = false;
index bb5dfc410a667fc226154968b5134b395e51792d..215543575f477c9a981e18f8bc0f40b2ed827572 100644 (file)
@@ -533,7 +533,7 @@ static int psp_v11_0_memory_training(struct psp_context *psp, uint32_t ops)
                        }
 
                        memcpy_toio(adev->mman.aper_base_kaddr, buf, sz);
-                       adev->hdp.funcs->flush_hdp(adev, NULL);
+                       amdgpu_device_flush_hdp(adev, NULL);
                        vfree(buf);
                        drm_dev_exit(idx);
                } else {
index 17f1ccd8bd534301d0b00930af896a2f5abfe0ba..f5f616ab20e7049794af60994a09c78d83e1e748 100644 (file)
@@ -610,7 +610,7 @@ static int psp_v13_0_memory_training(struct psp_context *psp, uint32_t ops)
                        }
 
                        memcpy_toio(adev->mman.aper_base_kaddr, buf, sz);
-                       adev->hdp.funcs->flush_hdp(adev, NULL);
+                       amdgpu_device_flush_hdp(adev, NULL);
                        vfree(buf);
                        drm_dev_exit(idx);
                } else {
index 7c49c3f3c3881ee0cddc934e6fe57f0eef01e443..256288c6cd78ef968130f368676adea484532776 100644 (file)
@@ -498,7 +498,7 @@ static int psp_v14_0_memory_training(struct psp_context *psp, uint32_t ops)
                        }
 
                        memcpy_toio(adev->mman.aper_base_kaddr, buf, sz);
-                       adev->hdp.funcs->flush_hdp(adev, NULL);
+                       amdgpu_device_flush_hdp(adev, NULL);
                        vfree(buf);
                        drm_dev_exit(idx);
                } else {