serial: 8250: of: Add new port type for MediaTek BTIF controller on MT7622/23 SoC

MediaTek BTIF controller is the serial interface similar to UART but it
works only as the digital device which is mainly used to communicate with
the connectivity module called CONNSYS inside the SoC which could be mostly
found on those MediaTek SoCs with Bluetooth feature such as MT7622 and
MT7623 SoCs.

And the controller is made as being compatible with the 8250 register
layout with extra registers such as DMA enablement so it tends to be
integrated with reusing 8250 OF driver. However, DMA mode is not being
supported yet in the current driver.

Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Suggested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/tty/serial/8250/8250_of.c b/drivers/tty/serial/8250/8250_of.c
index 30eacbffaa51a83da94b6680dee0b167a9aecc0b..1222c005fb9889ea21f279882f43c27da5a34c43 100644 (file)
--- a/drivers/tty/serial/8250/8250_of.c
+++ b/drivers/tty/serial/8250/8250_of.c
@@ -313,6 +313,8 @@ static const struct of_device_id of_platform_serial_table[] = {
                .data = (void *)PORT_ALTR_16550_F64, },
        { .compatible = "altr,16550-FIFO128",
                .data = (void *)PORT_ALTR_16550_F128, },
+       { .compatible = "mediatek,mtk-btif",
+               .data = (void *)PORT_MTK_BTIF, },
        { .compatible = "mrvl,mmp-uart",
                .data = (void *)PORT_XSCALE, },
        { .compatible = "ti,da830-uart", .data = (void *)PORT_DA830, },

diff --git a/drivers/tty/serial/8250/8250_port.c b/drivers/tty/serial/8250/8250_port.c
index 6b745e440b81b71bcd874354f21a4fa6ec19e394..4726aa27696824583809ce520324e0452402dfd1 100644 (file)
--- a/drivers/tty/serial/8250/8250_port.c
+++ b/drivers/tty/serial/8250/8250_port.c
@@ -289,6 +289,14 @@ static const struct serial8250_config uart_config[] = {
                .rxtrig_bytes   = {1, 4, 8, 14},
                .flags          = UART_CAP_FIFO | UART_CAP_AFE,
        },
+       [PORT_MTK_BTIF] = {
+               .name           = "MediaTek BTIF",
+               .fifo_size      = 16,
+               .tx_loadsz      = 16,
+               .fcr            = UART_FCR_ENABLE_FIFO |
+                                 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
+               .flags          = UART_CAP_FIFO,
+       },
 };
 
 /* Uart divisor latch read */

diff --git a/include/uapi/linux/serial_core.h b/include/uapi/linux/serial_core.h
index dc2d7cb766ab3c51cb8bae9faebb0edca998159c..50d71c436323918f2ca2a20dd3d7c1d8016392eb 100644 (file)
--- a/include/uapi/linux/serial_core.h
+++ b/include/uapi/linux/serial_core.h
@@ -274,4 +274,7 @@
 /* MPS2 UART */
 #define PORT_MPS2UART  116
 
+/* MediaTek BTIF */
+#define PORT_MTK_BTIF  117
+
 #endif /* _UAPILINUX_SERIAL_CORE_H */