drm/xe: Always write GEN12_RCU_MODE.GEN12_RCU_MODE_CCS_ENABLE for CCS engines

If CCS0 was fused we did not write this register thus CCS engine were
not enabled resulting in driver load failures.

Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
index 63a4efd5edccd5fc323d98b76b426829f8c66135..4b56c35b988d409d0d1ec949f9a10f2e0e601714 100644 (file)
--- a/drivers/gpu/drm/xe/xe_hw_engine.c
+++ b/drivers/gpu/drm/xe/xe_hw_engine.c
@@ -253,7 +253,7 @@ void xe_hw_engine_enable_ring(struct xe_hw_engine *hwe)
        u32 ccs_mask =
                xe_hw_engine_mask_per_class(hwe->gt, XE_ENGINE_CLASS_COMPUTE);
 
-       if (hwe->class == XE_ENGINE_CLASS_COMPUTE && ccs_mask & BIT(0))
+       if (hwe->class == XE_ENGINE_CLASS_COMPUTE && ccs_mask)
                xe_mmio_write32(hwe->gt, GEN12_RCU_MODE.reg,
                                _MASKED_BIT_ENABLE(GEN12_RCU_MODE_CCS_ENABLE));