Add an INFO query to check if user queues are supported.
v2: switch to a mask of IPs (Marek)
v3: move to drm_amdgpu_info_device (Marek)
Cc: marek.olsak@amd.com
Cc: prike.liang@amd.com
Cc: sunil.khatri@amd.com
Cc: yogesh.mohanmarimuthu@amd.com
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Sunil Khatri <sunil.khatri@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
}
}
+ if (adev->userq_funcs[AMDGPU_HW_IP_GFX])
+ dev_info->userq_ip_mask |= (1 << AMDGPU_HW_IP_GFX);
+ if (adev->userq_funcs[AMDGPU_HW_IP_COMPUTE])
+ dev_info->userq_ip_mask |= (1 << AMDGPU_HW_IP_COMPUTE);
+ if (adev->userq_funcs[AMDGPU_HW_IP_DMA])
+ dev_info->userq_ip_mask |= (1 << AMDGPU_HW_IP_DMA);
+
ret = copy_to_user(out, dev_info,
min((size_t)size, sizeof(*dev_info))) ? -EFAULT : 0;
kfree(dev_info);
__u32 csa_size;
/* context save area base virtual alignment for gfx11 */
__u32 csa_alignment;
+ /* Userq IP mask (1 << AMDGPU_HW_IP_*) */
+ __u32 userq_ip_mask;
+ __u32 pad;
};
struct drm_amdgpu_info_hw_ip {