drm/amdgpu: add UAPI to query if user queues are supported
authorAlex Deucher <alexander.deucher@amd.com>
Mon, 24 Mar 2025 20:26:00 +0000 (16:26 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Tue, 8 Apr 2025 20:48:22 +0000 (16:48 -0400)
Add an INFO query to check if user queues are supported.

v2: switch to a mask of IPs (Marek)
v3: move to drm_amdgpu_info_device (Marek)

Cc: marek.olsak@amd.com
Cc: prike.liang@amd.com
Cc: sunil.khatri@amd.com
Cc: yogesh.mohanmarimuthu@amd.com
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Sunil Khatri <sunil.khatri@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
include/uapi/drm/amdgpu_drm.h

index f8370da080388a0c86f21eb1d93d773101e1cb3e..b64a21773230c02e560d1a8e921c602348b90f9b 100644 (file)
@@ -999,6 +999,13 @@ out:
                        }
                }
 
+               if (adev->userq_funcs[AMDGPU_HW_IP_GFX])
+                       dev_info->userq_ip_mask |= (1 << AMDGPU_HW_IP_GFX);
+               if (adev->userq_funcs[AMDGPU_HW_IP_COMPUTE])
+                       dev_info->userq_ip_mask |= (1 << AMDGPU_HW_IP_COMPUTE);
+               if (adev->userq_funcs[AMDGPU_HW_IP_DMA])
+                       dev_info->userq_ip_mask |= (1 << AMDGPU_HW_IP_DMA);
+
                ret = copy_to_user(out, dev_info,
                                   min((size_t)size, sizeof(*dev_info))) ? -EFAULT : 0;
                kfree(dev_info);
index 5dbd9037afe7532e0b1eb747d1e87c21c9f75d99..ef97c0d78b8a038edc2e9b1bc7203713c6c280d2 100644 (file)
@@ -1453,6 +1453,9 @@ struct drm_amdgpu_info_device {
        __u32 csa_size;
        /* context save area base virtual alignment for gfx11 */
        __u32 csa_alignment;
+       /* Userq IP mask (1 << AMDGPU_HW_IP_*) */
+       __u32 userq_ip_mask;
+       __u32 pad;
 };
 
 struct drm_amdgpu_info_hw_ip {