drm/amd/display: Remove redundant checks for res_pool->dccg

The null checks for res_pool->dccg are redundant as it was already
dereferenced previously, as reported by Coverity; therefore the
null checks are removed.

This fixes 6 REVERSE_INULL issues reported by Coverity.

Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c
index 86d871cc74c7f13b7cf04bcf4e5d0ea966602df8..f96adc689055cc1a15d8109d12b212acc61e6e27 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c
@@ -240,7 +240,7 @@ void dcn201_init_hw(struct dc *dc)
                res_pool->ref_clocks.xtalin_clock_inKhz =
                        dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
 
-               if (res_pool->dccg && res_pool->hubbub) {
+               if (res_pool->hubbub) {
                        (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,
                                        dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,
                                        &res_pool->ref_clocks.dccg_ref_clock_inKhz);

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
index 4c4706153305097e36945a880c54fba60d3bd554..bcacfd893cf7e27a8cfbee59614ede314a3c353e 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
@@ -656,7 +656,7 @@ void dcn30_init_hw(struct dc *dc)
                res_pool->ref_clocks.xtalin_clock_inKhz =
                                dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
 
-               if (res_pool->dccg && res_pool->hubbub) {
+               if (res_pool->hubbub) {
 
                        (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,
                                        dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
index 1c8abb417b6e0dc056594ec0a11c4f7903b58e85..746c522adf84cad68dcf63cf29df9b8c042499d0 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
@@ -132,7 +132,7 @@ void dcn31_init_hw(struct dc *dc)
                res_pool->ref_clocks.xtalin_clock_inKhz =
                                dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
 
-               if (res_pool->dccg && res_pool->hubbub) {
+               if (res_pool->hubbub) {
 
                        (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,
                                        dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
index 51dfda0e4df92588344d17a1c44c25a048f89d6b..aaeeb0ff4d849e61bd499e7da84907781df7623b 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
@@ -806,7 +806,7 @@ void dcn32_init_hw(struct dc *dc)
                res_pool->ref_clocks.xtalin_clock_inKhz =
                                dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
 
-               if (res_pool->dccg && res_pool->hubbub) {
+               if (res_pool->hubbub) {
                        (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,
                                        dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,
                                        &res_pool->ref_clocks.dccg_ref_clock_inKhz);

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
index 0602921399cd182dd95c5c2339265e74151da93b..e4f7078c10269ff9c6ed452dc1f3fdcd969ca775 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
@@ -188,7 +188,7 @@ void dcn35_init_hw(struct dc *dc)
                res_pool->ref_clocks.xtalin_clock_inKhz =
                                dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
 
-               if (res_pool->dccg && res_pool->hubbub) {
+               if (res_pool->hubbub) {
 
                        (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,
                                dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
index ebe55b74ca3f32633089d80c4e6c37607422502d..7a456618f31328eefc5c231a1f7f2e73e70bdc4b 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
@@ -259,7 +259,7 @@ void dcn401_init_hw(struct dc *dc)
                res_pool->ref_clocks.xtalin_clock_inKhz =
                                dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
 
-               if (res_pool->dccg && res_pool->hubbub) {
+               if (res_pool->hubbub) {
                        (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,
                                        dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,
                                        &res_pool->ref_clocks.dccg_ref_clock_inKhz);