arm64: dts: ti: k3-j721e-beagleboneai64: Fix reversed C6x carveout locations

The DMA carveout for the C6x core 0 is at 0xa6000000 and core 1 is at
0xa7000000. These are reversed in DT. While both C6x can access either
region, so this is not normally a problem, but if we start restricting
the memory each core can access (such as with firewalls) the cores
accessing the regions for the wrong core will not work. Fix this here.

Fixes: fae14a1cb8dd ("arm64: dts: ti: Add k3-j721e-beagleboneai64")
Signed-off-by: Andrew Davis <afd@ti.com>
Link: https://lore.kernel.org/r/20240801181232.55027-2-afd@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>

diff --git a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
index a2925555fe818085fd64a7e52c5f14dbfc504e93..fb899c99753ecdd3c1c4a3d7749d364c33b9e9e1 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
@@ -123,7 +123,7 @@
                        no-map;
                };
 
-               c66_1_dma_memory_region: c66-dma-memory@a6000000 {
+               c66_0_dma_memory_region: c66-dma-memory@a6000000 {
                        compatible = "shared-dma-pool";
                        reg = <0x00 0xa6000000 0x00 0x100000>;
                        no-map;
@@ -135,7 +135,7 @@
                        no-map;
                };
 
-               c66_0_dma_memory_region: c66-dma-memory@a7000000 {
+               c66_1_dma_memory_region: c66-dma-memory@a7000000 {
                        compatible = "shared-dma-pool";
                        reg = <0x00 0xa7000000 0x00 0x100000>;
                        no-map;