ASoC: SOF: intel: add snd_sof_dsp_check_sdw_irq ops
authorBard Liao <yung-chuan.liao@linux.intel.com>
Fri, 23 Jul 2021 11:54:50 +0000 (19:54 +0800)
committerMark Brown <broonie@kernel.org>
Mon, 2 Aug 2021 14:45:40 +0000 (15:45 +0100)
SoundWire IRQ status checks are platform-dependent, add new ops structure
to provide abstraction.

Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
Link: https://lore.kernel.org/r/20210723115451.7245-6-yung-chuan.liao@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
sound/soc/sof/intel/cnl.c
sound/soc/sof/intel/hda.c
sound/soc/sof/intel/hda.h
sound/soc/sof/intel/icl.c
sound/soc/sof/intel/shim.h
sound/soc/sof/intel/tgl.c

index acc07cfbc8e387445ce8168a469d725aa81a28be..e115e12a856fda3ec24402d6c072903cf0d37b51 100644 (file)
@@ -349,6 +349,7 @@ const struct sof_intel_dsp_desc cnl_chip_info = {
        .ssp_base_offset = CNL_SSP_BASE_OFFSET,
        .sdw_shim_base = SDW_SHIM_BASE,
        .sdw_alh_base = SDW_ALH_BASE,
+       .check_sdw_irq  = hda_common_check_sdw_irq,
 };
 EXPORT_SYMBOL_NS(cnl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
 
@@ -367,5 +368,6 @@ const struct sof_intel_dsp_desc jsl_chip_info = {
        .ssp_base_offset = CNL_SSP_BASE_OFFSET,
        .sdw_shim_base = SDW_SHIM_BASE,
        .sdw_alh_base = SDW_ALH_BASE,
+       .check_sdw_irq  = hda_common_check_sdw_irq,
 };
 EXPORT_SYMBOL_NS(jsl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
index 79388489c4e2027b68eb9544a6e4d7f728320849..c979581c6812c26b34a1074d42b2f47a2aafe438 100644 (file)
@@ -222,7 +222,7 @@ static int hda_sdw_exit(struct snd_sof_dev *sdev)
        return 0;
 }
 
-static bool hda_dsp_check_sdw_irq(struct snd_sof_dev *sdev)
+bool hda_common_check_sdw_irq(struct snd_sof_dev *sdev)
 {
        struct sof_intel_hda_dev *hdev;
        bool ret = false;
@@ -248,6 +248,17 @@ out:
        return ret;
 }
 
+static bool hda_dsp_check_sdw_irq(struct snd_sof_dev *sdev)
+{
+       const struct sof_intel_dsp_desc *chip;
+
+       chip = get_chip_info(sdev->pdata);
+       if (chip && chip->check_sdw_irq)
+               return chip->check_sdw_irq(sdev);
+
+       return false;
+}
+
 static irqreturn_t hda_dsp_sdw_thread(int irq, void *context)
 {
        return sdw_intel_thread(irq, context);
index 06ea0006999a1aef116d3ed3406b89742031446b..4fdfb108645c52fb75adde2b94ccfcadcf5a844a 100644 (file)
@@ -691,6 +691,7 @@ int hda_dsp_trace_trigger(struct snd_sof_dev *sdev, int cmd);
 int hda_sdw_startup(struct snd_sof_dev *sdev);
 void hda_sdw_int_enable(struct snd_sof_dev *sdev, bool enable);
 void hda_sdw_process_wakeen(struct snd_sof_dev *sdev);
+bool hda_common_check_sdw_irq(struct snd_sof_dev *sdev);
 
 #else
 
@@ -736,6 +737,12 @@ static inline bool hda_sdw_check_wakeen_irq(struct snd_sof_dev *sdev)
 static inline void hda_sdw_process_wakeen(struct snd_sof_dev *sdev)
 {
 }
+
+static inline bool hda_common_check_sdw_irq(struct snd_sof_dev *sdev)
+{
+       return false;
+}
+
 #endif
 
 /* common dai driver */
index 74a14b24794ce827359765d178989b5252235866..ee095b8f2d01cacba6279bb26d9cc4e1d4e7fd7a 100644 (file)
@@ -144,5 +144,6 @@ const struct sof_intel_dsp_desc icl_chip_info = {
        .ssp_base_offset = CNL_SSP_BASE_OFFSET,
        .sdw_shim_base = SDW_SHIM_BASE,
        .sdw_alh_base = SDW_ALH_BASE,
+       .check_sdw_irq  = hda_common_check_sdw_irq,
 };
 EXPORT_SYMBOL_NS(icl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
index ee031248d834e1db06fc5b9fcef09af1502a8922..e9f7d4d7fcce823126eafd93f5184ddc7e1059b4 100644 (file)
@@ -166,6 +166,7 @@ struct sof_intel_dsp_desc {
        int ssp_base_offset;            /* base address of the SSPs */
        u32 sdw_shim_base;
        u32 sdw_alh_base;
+       bool (*check_sdw_irq)(struct snd_sof_dev *sdev);
 };
 
 extern const struct snd_sof_dsp_ops sof_tng_ops;
index 73aa45bc6f2b0c59b1561c9fcf55fe1fee66353b..199d41a7dc9bfbd06dd483b61493fb4eb01a35a6 100644 (file)
@@ -139,6 +139,7 @@ const struct sof_intel_dsp_desc tgl_chip_info = {
        .ssp_base_offset = CNL_SSP_BASE_OFFSET,
        .sdw_shim_base = SDW_SHIM_BASE,
        .sdw_alh_base = SDW_ALH_BASE,
+       .check_sdw_irq  = hda_common_check_sdw_irq,
 };
 EXPORT_SYMBOL_NS(tgl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
 
@@ -157,6 +158,7 @@ const struct sof_intel_dsp_desc tglh_chip_info = {
        .ssp_base_offset = CNL_SSP_BASE_OFFSET,
        .sdw_shim_base = SDW_SHIM_BASE,
        .sdw_alh_base = SDW_ALH_BASE,
+       .check_sdw_irq  = hda_common_check_sdw_irq,
 };
 EXPORT_SYMBOL_NS(tglh_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
 
@@ -175,6 +177,7 @@ const struct sof_intel_dsp_desc ehl_chip_info = {
        .ssp_base_offset = CNL_SSP_BASE_OFFSET,
        .sdw_shim_base = SDW_SHIM_BASE,
        .sdw_alh_base = SDW_ALH_BASE,
+       .check_sdw_irq  = hda_common_check_sdw_irq,
 };
 EXPORT_SYMBOL_NS(ehl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
 
@@ -193,5 +196,6 @@ const struct sof_intel_dsp_desc adls_chip_info = {
        .ssp_base_offset = CNL_SSP_BASE_OFFSET,
        .sdw_shim_base = SDW_SHIM_BASE,
        .sdw_alh_base = SDW_ALH_BASE,
+       .check_sdw_irq  = hda_common_check_sdw_irq,
 };
 EXPORT_SYMBOL_NS(adls_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);