drm/msm/dpu: merge DPU_SSPP_SCALER_QSEED3, QSEED3LITE, QSEED4

Three different features, DPU_SSPP_SCALER_QSEED3, QSEED3LITE and QSEED4
are all related to different versions of the same HW scaling block.
Corresponding driver parts use scaler_blk.version to identify the
correct way to program the hardware. In order to simplify the driver
codepath, merge these three feature bits into QSEED3_COMPATIBLE bin.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/570114/
Link: https://lore.kernel.org/r/20231201234234.2065610-10-dmitry.baryshkov@linaro.org

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index b8ea33d0f364fa35c83584f22e701c6e99815331..c24817b0e4e5d8b9678144eefd1b23d0c321f7ac 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -22,19 +22,19 @@
        BIT(DPU_SSPP_CSC_10BIT))
 
 #define VIG_MSM8998_MASK \
-       (VIG_MASK | BIT(DPU_SSPP_SCALER_QSEED3))
+       (VIG_MASK | BIT(DPU_SSPP_SCALER_QSEED3_COMPATIBLE))
 
 #define VIG_SDM845_MASK \
-       (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3))
+       (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3_COMPATIBLE))
 
 #define VIG_SDM845_MASK_SDMA \
        (VIG_SDM845_MASK | BIT(DPU_SSPP_SMART_DMA_V2))
 
 #define VIG_SC7180_MASK \
-       (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED4))
+       (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3_COMPATIBLE))
 
 #define VIG_SM6125_MASK \
-       (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3LITE))
+       (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3_COMPATIBLE))
 
 #define VIG_SC7180_MASK_SDMA \
        (VIG_SC7180_MASK | BIT(DPU_SSPP_SMART_DMA_V2))

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index f9586ddbafdad88de0bb2e9eb5bab0facaf549d5..d6b9000b63b07882a5509f82cce8610856ae0d6a 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -51,9 +51,7 @@ enum {
 /**
  * SSPP sub-blocks/features
  * @DPU_SSPP_SCALER_QSEED2,  QSEED2 algorithm support
- * @DPU_SSPP_SCALER_QSEED3,  QSEED3 alogorithm support
- * @DPU_SSPP_SCALER_QSEED3LITE,  QSEED3 Lite alogorithm support
- * @DPU_SSPP_SCALER_QSEED4,  QSEED4 algorithm support
+ * @DPU_SSPP_SCALER_QSEED3_COMPATIBLE,  QSEED3-compatible alogorithm support (includes QSEED3, QSEED3LITE and QSEED4)
  * @DPU_SSPP_SCALER_RGB,     RGB Scaler, supported by RGB pipes
  * @DPU_SSPP_CSC,            Support of Color space converion
  * @DPU_SSPP_CSC_10BIT,      Support of 10-bit Color space conversion
@@ -71,9 +69,7 @@ enum {
  */
 enum {
        DPU_SSPP_SCALER_QSEED2 = 0x1,
-       DPU_SSPP_SCALER_QSEED3,
-       DPU_SSPP_SCALER_QSEED3LITE,
-       DPU_SSPP_SCALER_QSEED4,
+       DPU_SSPP_SCALER_QSEED3_COMPATIBLE,
        DPU_SSPP_SCALER_RGB,
        DPU_SSPP_CSC,
        DPU_SSPP_CSC_10BIT,

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
index b408d456c123dabc7becda7f710d327cd39901b1..26307d9fc81d02f3198e8d78cf933c22c6394f9b 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
@@ -605,9 +605,7 @@ static void _setup_layer_ops(struct dpu_hw_sspp *c,
                test_bit(DPU_SSPP_SMART_DMA_V2, &c->cap->features))
                c->ops.setup_multirect = dpu_hw_sspp_setup_multirect;
 
-       if (test_bit(DPU_SSPP_SCALER_QSEED3, &features) ||
-                       test_bit(DPU_SSPP_SCALER_QSEED3LITE, &features) ||
-                       test_bit(DPU_SSPP_SCALER_QSEED4, &features))
+       if (test_bit(DPU_SSPP_SCALER_QSEED3_COMPATIBLE, &features))
                c->ops.setup_scaler = _dpu_hw_sspp_setup_scaler3;
 
        if (test_bit(DPU_SSPP_CDP, &features))
@@ -643,10 +641,7 @@ int _dpu_hw_sspp_init_debugfs(struct dpu_hw_sspp *hw_pipe, struct dpu_kms *kms,
                        cfg->len,
                        kms);
 
-       if (cfg->features & BIT(DPU_SSPP_SCALER_QSEED3) ||
-                       cfg->features & BIT(DPU_SSPP_SCALER_QSEED3LITE) ||
-                       cfg->features & BIT(DPU_SSPP_SCALER_QSEED2) ||
-                       cfg->features & BIT(DPU_SSPP_SCALER_QSEED4))
+       if (sblk->scaler_blk.len)
                dpu_debugfs_create_regset32("scaler_blk", 0400,
                                debugfs_root,
                                sblk->scaler_blk.base + cfg->base,

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index 93365332bdac2873308cd04d66caaebed590e084..4d7f3894f4d7be458b889348b7d09dfb050ae030 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -470,8 +470,7 @@ static void _dpu_plane_setup_scaler3(struct dpu_hw_sspp *pipe_hw,
                        scale_cfg->src_height[i] /= chroma_subsmpl_v;
                }
 
-               if (pipe_hw->cap->features &
-                       BIT(DPU_SSPP_SCALER_QSEED4)) {
+               if (pipe_hw->cap->sblk->scaler_blk.version >= 0x3000) {
                        scale_cfg->preload_x[i] = DPU_QSEED4_DEFAULT_PRELOAD_H;
                        scale_cfg->preload_y[i] = DPU_QSEED4_DEFAULT_PRELOAD_V;
                } else {