drm/amd/display: Support external tunneling feature

[Why & How]
The original code only supports the tunneling for embedded one.
To support external tunneling feature, it needs to check
Tunneling_Support bit register.

Reviewed-by: Wenjing Liu <wenjing.liu@amd.com>
Reviewed-by: Jun Lei <jun.lei@amd.com>
Signed-off-by: Cruise Hung <Cruise.Hung@amd.com>
Signed-off-by: Tom Chung <chiahsuan.chung@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 13559fe56062927d3f434854ad94dbd9f511ca53..15ef1f26864f951b4e48d7ee957f658c232e1863 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -3911,6 +3911,10 @@ enum dc_status resource_map_pool_resources(
                if (!dc->link_srv->dp_decide_link_settings(stream,
                                &pipe_ctx->link_config.dp_link_settings))
                        return DC_FAIL_DP_LINK_BANDWIDTH;
+
+               dc->link_srv->dp_decide_tunnel_settings(stream,
+                               &pipe_ctx->link_config.dp_tunnel_settings);
+
                if (dc->link_srv->dp_get_encoding_format(
                                &pipe_ctx->link_config.dp_link_settings) == DP_128b_132b_ENCODING) {
                        pipe_ctx->stream_res.hpo_dp_stream_enc =

diff --git a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
index 77c87ad5722078b1c060cea2c111805858e10715..0bad8304ccf60e091ae637c6d9e9f1b6f7673a5e 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
@@ -159,6 +159,11 @@ struct dc_link_settings {
        uint8_t link_rate_set;
 };
 
+struct dc_tunnel_settings {
+       bool should_enable_dp_tunneling;
+       bool should_use_dp_bw_allocation;
+};
+
 union dc_dp_ffe_preset {
        struct {
                uint8_t level           : 4;
@@ -943,10 +948,20 @@ union dpia_info {
        uint8_t raw;
 };
 
+/* DPCD[0xE0020] USB4_DRIVER_BW_CAPABILITY register. */
+union usb4_driver_bw_cap {
+       struct {
+               uint8_t rsvd :7;
+               uint8_t driver_bw_alloc_support :1;
+       } bits;
+       uint8_t raw;
+};
+
 /* DP Tunneling over USB4 */
 struct dpcd_usb4_dp_tunneling_info {
        union dp_tun_cap_support dp_tun_cap;
        union dpia_info dpia_info;
+       union usb4_driver_bw_cap driver_bw_cap;
        uint8_t usb4_driver_id;
        uint8_t usb4_topology_id[DPCD_USB4_TOPOLOGY_ID_LEN];
 };
@@ -1486,5 +1501,11 @@ struct dp_trace {
 # ifndef DP_TUNNELING_BW_ALLOC_CAP_CHANGED
 # define DP_TUNNELING_BW_ALLOC_CAP_CHANGED             (1 << 3)
 # endif
+# ifndef DPTX_BW_ALLOC_UNMASK_IRQ
+# define DPTX_BW_ALLOC_UNMASK_IRQ                      (1 << 6)
+# endif
+# ifndef DPTX_BW_ALLOC_MODE_ENABLE
+# define DPTX_BW_ALLOC_MODE_ENABLE                     (1 << 7)
+# endif
 
 #endif /* DC_DP_TYPES_H */

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
index 63077c1fad859c2b77511d868e90e3bd0207ce59..c814d957305adae7e20db81d37b2b8df068f0f98 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
@@ -1550,7 +1550,7 @@ static bool should_avoid_empty_tu(struct pipe_ctx *pipe_ctx)
        struct dc_link_settings *link_settings = &pipe_ctx->link_config.dp_link_settings;
        const struct dc *dc = pipe_ctx->stream->link->dc;
 
-       if (pipe_ctx->stream->link->ep_type != DISPLAY_ENDPOINT_USB4_DPIA)
+       if (pipe_ctx->link_config.dp_tunnel_settings.should_enable_dp_tunneling == false)
                return false;
 
        // Not necessary for MST configurations

diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
index 051bd83680d169af37b3cf57395466578620474d..faa1b4e619de6568fdbdc89ce85bea20dbdaa5d0 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
@@ -384,7 +384,9 @@ struct link_resource {
 
 struct link_config {
        struct dc_link_settings dp_link_settings;
+       struct dc_tunnel_settings dp_tunnel_settings;
 };
+
 union pipe_update_flags {
        struct {
                uint32_t enable : 1;

diff --git a/drivers/gpu/drm/amd/display/dc/inc/link.h b/drivers/gpu/drm/amd/display/dc/inc/link.h
index 2948a696ee12088dbc045c1e3e533e46b89dad47..7d16351bba9902cc1ede31094d5884b578cb4b08 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/link.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/link.h
@@ -207,6 +207,9 @@ struct link_service {
        bool (*dp_decide_link_settings)(
                struct dc_stream_state *stream,
                struct dc_link_settings *link_setting);
+       void (*dp_decide_tunnel_settings)(
+               struct dc_stream_state *stream,
+               struct dc_tunnel_settings *dp_tunnel_setting);
        enum dp_link_encoding (*mst_decide_link_encoding_format)(
                        const struct dc_link *link);
        bool (*edp_decide_link_settings)(struct dc_link *link,

diff --git a/drivers/gpu/drm/amd/display/dc/link/link_detection.c b/drivers/gpu/drm/amd/display/dc/link/link_detection.c
index cc9191a5c9e63116fec5ea1c9831b0f1e6d54851..9655e6fa53a4bf69d9a179410241c31b83326d67 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/link/link_detection.c
+++ b/drivers/gpu/drm/amd/display/dc/link/link_detection.c
@@ -611,6 +611,7 @@ static bool detect_dp(struct dc_link *link,
                link->dpcd_caps.dongle_type = sink_caps->dongle_type;
                link->dpcd_caps.is_dongle_type_one = sink_caps->is_dongle_type_one;
                link->dpcd_caps.dpcd_rev.raw = 0;
+               link->dpcd_caps.usb4_dp_tun_info.dp_tun_cap.raw = 0;
        }
 
        return true;
@@ -1007,21 +1008,11 @@ static bool detect_link_and_local_sink(struct dc_link *link,
                                        link->reported_link_cap.link_rate > LINK_RATE_HIGH3)
                                link->reported_link_cap.link_rate = LINK_RATE_HIGH3;
 
-                       /*
-                        * If this is DP over USB4 link then we need to:
-                        * - Enable BW ALLOC support on DPtx if applicable
-                        */
-                       if (dc->config.usb4_bw_alloc_support) {
-                               if (link_dp_dpia_set_dptx_usb4_bw_alloc_support(link)) {
-                                       /* update with non reduced link cap if bw allocation mode is supported */
-                                       if (link->dpia_bw_alloc_config.nrd_max_link_rate &&
-                                               link->dpia_bw_alloc_config.nrd_max_lane_count) {
-                                               link->reported_link_cap.link_rate =
-                                                       link->dpia_bw_alloc_config.nrd_max_link_rate;
-                                               link->reported_link_cap.lane_count =
-                                                       link->dpia_bw_alloc_config.nrd_max_lane_count;
-                                       }
-                               }
+                       if (link->dpcd_caps.usb4_dp_tun_info.dp_tun_cap.bits.dp_tunneling
+                                       && link->dpcd_caps.usb4_dp_tun_info.dp_tun_cap.bits.dpia_bw_alloc
+                                       && link->dpcd_caps.usb4_dp_tun_info.driver_bw_cap.bits.driver_bw_alloc_support) {
+                               if (link_dpia_enable_usb4_dp_bw_alloc_mode(link) == false)
+                                       link->dpcd_caps.usb4_dp_tun_info.dp_tun_cap.bits.dpia_bw_alloc = false;
                        }
                        break;
                }

diff --git a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
index 53c961f86d43c0957d829f04e34a935882e229ba..273a3be6d593af910e4b89a259c049d960540f8e 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
+++ b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
@@ -2374,7 +2374,7 @@ void link_set_dpms_off(struct pipe_ctx *pipe_ctx)
        update_psp_stream_config(pipe_ctx, true);
        dc->hwss.blank_stream(pipe_ctx);
 
-       if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA)
+       if (pipe_ctx->link_config.dp_tunnel_settings.should_use_dp_bw_allocation)
                deallocate_usb4_bandwidth(pipe_ctx->stream);
 
        if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
@@ -2442,7 +2442,7 @@ void link_set_dpms_off(struct pipe_ctx *pipe_ctx)
        if (link->connector_signal == SIGNAL_TYPE_EDP && dc->debug.psp_disabled_wa) {
                /* reset internal save state to default since eDP is  off */
                enum dp_panel_mode panel_mode = dp_get_panel_mode(pipe_ctx->stream->link);
-               /* since current psp not loaded, we need to reset it to default*/
+               /* since current psp not loaded, we need to reset it to default */
                link->panel_mode = panel_mode;
        }
 }
@@ -2620,7 +2620,7 @@ void link_set_dpms_on(
        if (dc_is_dp_signal(pipe_ctx->stream->signal))
                dp_set_hblank_reduction_on_rx(pipe_ctx);
 
-       if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA)
+       if (pipe_ctx->link_config.dp_tunnel_settings.should_use_dp_bw_allocation)
                allocate_usb4_bandwidth(pipe_ctx->stream);
 
        if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)

diff --git a/drivers/gpu/drm/amd/display/dc/link/link_factory.c b/drivers/gpu/drm/amd/display/dc/link/link_factory.c
index 0125f2cfc114aa18aeba2d12fde6b83b426c4408..1a04f4b7458593ed5560b143cd4fabc3c3cec425 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/link/link_factory.c
+++ b/drivers/gpu/drm/amd/display/dc/link/link_factory.c
@@ -156,6 +156,7 @@ static void construct_link_service_dp_capability(struct link_service *link_srv)
        link_srv->dp_get_encoding_format = link_dp_get_encoding_format;
        link_srv->dp_should_enable_fec = dp_should_enable_fec;
        link_srv->dp_decide_link_settings = link_decide_link_settings;
+       link_srv->dp_decide_tunnel_settings = link_decide_dp_tunnel_settings;
        link_srv->mst_decide_link_encoding_format =
                        mst_decide_link_encoding_format;
        link_srv->edp_decide_link_settings = edp_decide_link_settings;

diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
index 9d49e77a24a1f0649682309b769abf843b408bb1..8f79881ad9f1a9e15f246a98662c740da06855fd 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
@@ -2021,11 +2021,9 @@ static bool retrieve_link_cap(struct dc_link *link)
                        sizeof(link->dpcd_caps.max_uncompressed_pixel_rate_cap.raw));
 
        /* Read DP tunneling information. */
-       if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) {
-               status = dpcd_get_tunneling_device_data(link);
-               if (status != DC_OK)
-                       dm_error("%s: Read DP tunneling device data failed.\n", __func__);
-       }
+       status = dpcd_get_tunneling_device_data(link);
+       if (status != DC_OK)
+               dm_error("%s: Read DP tunneling device data failed.\n", __func__);
 
        retrieve_cable_id(link);
        dpcd_write_cable_id_to_dprx(link);

diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia.c
index c149210096ac723026a06380df6cf5849224c156..22bfdced64ab6afb82f82a143890b1be70e294dc 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia.c
@@ -62,6 +62,36 @@ enum dc_status dpcd_get_tunneling_device_data(struct dc_link *link)
        if (status != DC_OK)
                goto err;
 
+       link->dpcd_caps.usb4_dp_tun_info.dp_tun_cap.raw =
+                       dpcd_dp_tun_data[DP_TUNNELING_CAPABILITIES_SUPPORT - DP_TUNNELING_CAPABILITIES_SUPPORT];
+
+       if (link->dpcd_caps.usb4_dp_tun_info.dp_tun_cap.bits.dp_tunneling == false)
+               goto err;
+
+       link->dpcd_caps.usb4_dp_tun_info.dpia_info.raw =
+                       dpcd_dp_tun_data[DP_IN_ADAPTER_INFO - DP_TUNNELING_CAPABILITIES_SUPPORT];
+       link->dpcd_caps.usb4_dp_tun_info.usb4_driver_id =
+                       dpcd_dp_tun_data[DP_USB4_DRIVER_ID - DP_TUNNELING_CAPABILITIES_SUPPORT];
+
+       if (link->dpcd_caps.usb4_dp_tun_info.dp_tun_cap.bits.dpia_bw_alloc) {
+               status = core_link_read_dpcd(link, USB4_DRIVER_BW_CAPABILITY,
+                               dpcd_dp_tun_data, 1);
+
+               if (status != DC_OK)
+                       goto err;
+
+               link->dpcd_caps.usb4_dp_tun_info.driver_bw_cap.raw = dpcd_dp_tun_data[0];
+       }
+
+       DC_LOG_DEBUG("%s: Link[%d]  DP tunneling support  (RouterId=%d  AdapterId=%d)  "
+                       "DPIA_BW_Alloc_support=%d "
+                       "CM_BW_Alloc_support=%d ",
+                       __func__, link->link_index,
+                       link->dpcd_caps.usb4_dp_tun_info.usb4_driver_id,
+                       link->dpcd_caps.usb4_dp_tun_info.dpia_info.bits.dpia_num,
+                       link->dpcd_caps.usb4_dp_tun_info.dp_tun_cap.bits.dpia_bw_alloc,
+                       link->dpcd_caps.usb4_dp_tun_info.driver_bw_cap.bits.driver_bw_alloc_support);
+
        status = core_link_read_dpcd(
                        link,
                        DP_USB4_ROUTER_TOPOLOGY_ID,
@@ -71,13 +101,6 @@ enum dc_status dpcd_get_tunneling_device_data(struct dc_link *link)
        if (status != DC_OK)
                goto err;
 
-       link->dpcd_caps.usb4_dp_tun_info.dp_tun_cap.raw =
-                       dpcd_dp_tun_data[DP_TUNNELING_CAPABILITIES_SUPPORT - DP_TUNNELING_CAPABILITIES_SUPPORT];
-       link->dpcd_caps.usb4_dp_tun_info.dpia_info.raw =
-                       dpcd_dp_tun_data[DP_IN_ADAPTER_INFO - DP_TUNNELING_CAPABILITIES_SUPPORT];
-       link->dpcd_caps.usb4_dp_tun_info.usb4_driver_id =
-                       dpcd_dp_tun_data[DP_USB4_DRIVER_ID - DP_TUNNELING_CAPABILITIES_SUPPORT];
-
        for (i = 0; i < DPCD_USB4_TOPOLOGY_ID_LEN; i++)
                link->dpcd_caps.usb4_dp_tun_info.usb4_topology_id[i] = dpcd_topology_data[i];
 
@@ -120,3 +143,20 @@ bool dpia_query_hpd_status(struct dc_link *link)
        return link->hpd_status;
 }
 
+void link_decide_dp_tunnel_settings(struct dc_stream_state *stream,
+                       struct dc_tunnel_settings *dp_tunnel_setting)
+{
+       struct dc_link *link = stream->link;
+
+       memset(dp_tunnel_setting, 0, sizeof(*dp_tunnel_setting));
+
+       if ((stream->signal == SIGNAL_TYPE_DISPLAY_PORT) || (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)) {
+               dp_tunnel_setting->should_enable_dp_tunneling =
+                                       link->dpcd_caps.usb4_dp_tun_info.dp_tun_cap.bits.dp_tunneling;
+
+               if (link->dpcd_caps.usb4_dp_tun_info.dp_tun_cap.bits.dpia_bw_alloc
+                               && link->dpcd_caps.usb4_dp_tun_info.driver_bw_cap.bits.driver_bw_alloc_support)
+                       dp_tunnel_setting->should_use_dp_bw_allocation = true;
+       }
+}
+

diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia.h b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia.h
index 363f45a1a9644770119e6d47ed2f1048d70e98d6..a61edfc9ca7aaa18a4b28154615d5635604229c5 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia.h
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia.h
@@ -38,4 +38,10 @@ enum dc_status dpcd_get_tunneling_device_data(struct dc_link *link);
  * Returns true if HPD high.
  */
 bool dpia_query_hpd_status(struct dc_link *link);
+
+/* Decide the DP tunneling settings based on the DPCD capabilities
+ */
+void link_decide_dp_tunnel_settings(struct dc_stream_state *stream,
+                       struct dc_tunnel_settings *dp_tunnel_setting);
+
 #endif /* __DC_LINK_DPIA_H__ */

diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c
index a254ead2f7e80addeb75b8d8a0e257326f997e8d..3af7564a84f107a249459bc7834203899fd27e84 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c
@@ -46,9 +46,10 @@
  */
 static bool link_dp_is_bw_alloc_available(struct dc_link *link)
 {
-       return (link && link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA
-               && link->hpd_status
-               && link->dpia_bw_alloc_config.bw_alloc_enabled);
+       return (link && link->hpd_status
+               && link->dpcd_caps.usb4_dp_tun_info.dp_tun_cap.bits.dp_tunneling
+               && link->dpcd_caps.usb4_dp_tun_info.dp_tun_cap.bits.dpia_bw_alloc
+               && link->dpcd_caps.usb4_dp_tun_info.driver_bw_cap.bits.driver_bw_alloc_support);
 }
 
 static void reset_bw_alloc_struct(struct dc_link *link)
@@ -141,7 +142,7 @@ static int get_non_reduced_max_lane_count(struct dc_link *link)
  * granuality, Driver_ID, CM_Group, & populate the BW allocation structs
  * for host router and dpia
  */
-static void init_usb4_bw_struct(struct dc_link *link)
+static void retrieve_usb4_dp_bw_allocation_info(struct dc_link *link)
 {
        reset_bw_alloc_struct(link);
 
@@ -282,49 +283,26 @@ static void link_dpia_send_bw_alloc_request(struct dc_link *link, int req_bw)
 // ------------------------------------------------------------------
 // PUBLIC FUNCTIONS
 // ------------------------------------------------------------------
-bool link_dp_dpia_set_dptx_usb4_bw_alloc_support(struct dc_link *link)
+bool link_dpia_enable_usb4_dp_bw_alloc_mode(struct dc_link *link)
 {
        bool ret = false;
-       uint8_t response = 0,
-                       bw_support_dpia = 0,
-                       bw_support_cm = 0;
+       uint8_t val;
 
-       if (!(link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA && link->hpd_status))
-               goto out;
+       if (link->hpd_status) {
+               val = DPTX_BW_ALLOC_MODE_ENABLE | DPTX_BW_ALLOC_UNMASK_IRQ;
 
-       if (core_link_read_dpcd(
-                       link,
-                       DP_TUNNELING_CAPABILITIES,
-                       &response,
-                       sizeof(uint8_t)) == DC_OK)
-               bw_support_dpia = (response >> 7) & 1;
-
-       if (core_link_read_dpcd(
-               link,
-               USB4_DRIVER_BW_CAPABILITY,
-               &response,
-               sizeof(uint8_t)) == DC_OK)
-               bw_support_cm = (response >> 7) & 1;
-
-       /* Send request acknowledgment to Turn ON DPTX support */
-       if (bw_support_cm && bw_support_dpia) {
-
-               response = 0x80;
-               if (core_link_write_dpcd(
-                               link,
-                               DPTX_BW_ALLOCATION_MODE_CONTROL,
-                               &response,
-                               sizeof(uint8_t)) != DC_OK) {
-                       DC_LOG_DEBUG("%s: FAILURE Enabling DPtx BW Allocation Mode Support for link(%d)\n",
-                               __func__, link->link_index);
-               } else {
-                       // SUCCESS Enabled DPtx BW Allocation Mode Support
-                       DC_LOG_DEBUG("%s: SUCCESS Enabling DPtx BW Allocation Mode Support for link(%d)\n",
-                               __func__, link->link_index);
+               if (core_link_write_dpcd(link, DPTX_BW_ALLOCATION_MODE_CONTROL, &val, sizeof(uint8_t)) == DC_OK) {
+                       DC_LOG_DEBUG("%s:  link[%d] DPTX BW allocation mode enabled", __func__, link->link_index);
+
+                       retrieve_usb4_dp_bw_allocation_info(link);
+
+                       if (link->dpia_bw_alloc_config.nrd_max_link_rate && link->dpia_bw_alloc_config.nrd_max_lane_count) {
+                               link->reported_link_cap.link_rate = link->dpia_bw_alloc_config.nrd_max_link_rate;
+                               link->reported_link_cap.lane_count = link->dpia_bw_alloc_config.nrd_max_lane_count;
+                       }
 
-                       ret = true;
-                       init_usb4_bw_struct(link);
                        link->dpia_bw_alloc_config.bw_alloc_enabled = true;
+                       ret = true;
 
                        /*
                         * During DP tunnel creation, CM preallocates BW and reduces estimated BW of other
@@ -332,11 +310,12 @@ bool link_dp_dpia_set_dptx_usb4_bw_alloc_support(struct dc_link *link)
                         * to make the CM to release preallocation and update estimated BW correctly for
                         * all DPIAs per host router
                         */
+                       // TODO: Zero allocation can be removed once the MSFT CM fix has been released
                        link_dp_dpia_allocate_usb4_bandwidth_for_stream(link, 0);
-               }
+               } else
+                       DC_LOG_DEBUG("%s:  link[%d] failed to enable DPTX BW allocation mode", __func__, link->link_index);
        }
 
-out:
        return ret;
 }
 
@@ -378,7 +357,8 @@ void link_dp_dpia_handle_bw_alloc_status(struct dc_link *link, uint8_t status)
  */
 void dpia_handle_usb4_bandwidth_allocation_for_link(struct dc_link *link, int peak_bw)
 {
-       if (link && link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA && link->dpia_bw_alloc_config.bw_alloc_enabled) {
+       if (link && link->dpcd_caps.usb4_dp_tun_info.dp_tun_cap.bits.dp_tunneling
+                       && link->dpia_bw_alloc_config.bw_alloc_enabled) {
                //1. Hot Plug
                if (link->hpd_status && peak_bw > 0) {
                        // If DP over USB4 then we need to check BW allocation
@@ -401,7 +381,7 @@ void link_dp_dpia_allocate_usb4_bandwidth_for_stream(struct dc_link *link, int r
        if (link_dp_is_bw_alloc_available(link))
                link_dpia_send_bw_alloc_request(link, req_bw);
        else
-               DC_LOG_DEBUG("%s:  Not able to send the BW Allocation request", __func__);
+               DC_LOG_DEBUG("%s:  BW Allocation mode not available", __func__);
 }
 
 bool dpia_validate_usb4_bw(struct dc_link **link, int *bw_needed_per_dpia, const unsigned int num_dpias)

diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.h b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.h
index 6df9b946b00feca538384601121a01c27b75bd1c..801965b5f9a4addb174a93b23c190386c838e9b8 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.h
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.h
@@ -43,13 +43,13 @@ enum bw_type {
 };
 
 /*
- * Enable BW Allocation Mode Support from the DP-Tx side
+ * Enable USB4 DP BW allocation mode
  *
  * @link: pointer to the dc_link struct instance
  *
  * return: SUCCESS or FAILURE
  */
-bool link_dp_dpia_set_dptx_usb4_bw_alloc_support(struct dc_link *link);
+bool link_dpia_enable_usb4_dp_bw_alloc_mode(struct dc_link *link);
 
 /*
  * Allocates only what the stream needs for bw, so if:

diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c
index 991b8ad4984b6c1e9169364854e7568a824e7600..6934774133471ff740891dc773e59b9dc853ff67 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c
@@ -352,7 +352,7 @@ enum dc_status dp_read_hpd_rx_irq_data(
                        irq_data->raw,
                        DP_SINK_STATUS - DP_SINK_COUNT + 1);
 
-               if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) {
+               if (link->dpcd_caps.usb4_dp_tun_info.dp_tun_cap.bits.dp_tunneling) {
                        retval = core_link_read_dpcd(
                                        link, DP_LINK_SERVICE_IRQ_VECTOR_ESI0,
                                        &irq_data->bytes.link_service_irq_esi0.raw, 1);
@@ -521,7 +521,7 @@ bool dp_handle_hpd_rx_irq(struct dc_link *link,
                dp_trace_link_loss_increment(link);
        }
 
-       if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) {
+       if (link->dpcd_caps.usb4_dp_tun_info.dp_tun_cap.bits.dp_tunneling) {
                if (hpd_irq_dpcd_data.bytes.link_service_irq_esi0.bits.DP_LINK_TUNNELING_IRQ)
                        dp_handle_tunneling_irq(link);
        }