PCI/ASPM: Save L1 PM Substates Capability for suspend/resume

4ff116d0d5fd ("PCI/ASPM: Save L1 PM Substates Capability for
suspend/resume") restored the L1 PM Substates Capability after resume,
which reduced power consumption by making the ASPM L1.x states work after
resume.

a7152be79b62 ("Revert "PCI/ASPM: Save L1 PM Substates Capability for
suspend/resume"") reverted 4ff116d0d5fd because resume failed on some
systems, so power consumption after resume increased again.

a7152be79b62 mentioned that we restore L1 PM substate configuration even
though ASPM L1 may already be enabled. This is due the fact that the
pci_restore_aspm_l1ss_state() was called before pci_restore_pcie_state().

Save and restore the L1 PM Substates Capability, following PCIe r6.1, sec
5.5.4 more closely by:

  1) Do not restore ASPM configuration in pci_restore_pcie_state() but
     do that after PCIe capability is restored in pci_restore_aspm_state()
     following PCIe r6.1, sec 5.5.4.

  2) If BIOS reenables L1SS, particularly L1.2, we need to clear the
     enables in the right order, downstream before upstream. Defer
     restoring the L1SS config until we are at the downstream component.
     Then update the config for both ends of the link in the prescribed
     order.

  3) Program ASPM L1 PM substate configuration before L1 enables.

  4) Program ASPM L1 PM substate enables last, after rest of the fields
     in the capability are programmed.

[bhelgaas: commit log, squash L1SS-related patches, do both LNKCTL restores
in pci_restore_pcie_state()]

Link: https://lore.kernel.org/r/20240128233212.1139663-3-david.e.box@linux.intel.com
Link: https://lore.kernel.org/r/20240128233212.1139663-4-david.e.box@linux.intel.com
Link: https://lore.kernel.org/r/20240223205851.114931-5-helgaas@kernel.org
Closes: https://bugzilla.kernel.org/show_bug.cgi?id=217321
Link: https://bugzilla.kernel.org/show_bug.cgi?id=216782
Link: https://bugzilla.kernel.org/show_bug.cgi?id=216877
Co-developed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Co-developed-by: David E. Box <david.e.box@linux.intel.com>
Reported-by: Koba Ko <koba.ko@canonical.com>
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: David E. Box <david.e.box@linux.intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Tested-by: Tasev Nikola <tasev.stefanoska@skynet.be> # Asus UX305FA
Cc: Mark Enriquez <enriquezmark36@gmail.com>
Cc: Thomas Witt <kernel@witt.link>
Cc: Werner Sembach <wse@tuxedocomputers.com>
Cc: Vidya Sagar <vidyas@nvidia.com>

diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 564e2cf2dde5392c743e993146953907df8a890c..ca6673588bc091e4fc8fed85a762f7aa11ed8307 100644 (file)
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -1623,6 +1623,8 @@ static int pci_save_pcie_state(struct pci_dev *dev)
        pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &cap[i++]);
        pcie_capability_read_word(dev, PCI_EXP_SLTCTL2, &cap[i++]);
 
+       pci_save_aspm_l1ss_state(dev);
+
        return 0;
 }
 
@@ -1630,7 +1632,7 @@ static void pci_restore_pcie_state(struct pci_dev *dev)
 {
        int i = 0;
        struct pci_cap_saved_state *save_state;
-       u16 *cap;
+       u16 *cap, lnkctl;
 
        save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
        if (!save_state)
@@ -1645,12 +1647,23 @@ static void pci_restore_pcie_state(struct pci_dev *dev)
 
        cap = (u16 *)&save_state->cap.data[0];
        pcie_capability_write_word(dev, PCI_EXP_DEVCTL, cap[i++]);
-       pcie_capability_write_word(dev, PCI_EXP_LNKCTL, cap[i++]);
+
+       /* Restore LNKCTL register with ASPM control field clear */
+       lnkctl = cap[i++];
+       pcie_capability_write_word(dev, PCI_EXP_LNKCTL,
+                                  lnkctl & ~PCI_EXP_LNKCTL_ASPMC);
+
        pcie_capability_write_word(dev, PCI_EXP_SLTCTL, cap[i++]);
        pcie_capability_write_word(dev, PCI_EXP_RTCTL, cap[i++]);
        pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, cap[i++]);
        pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, cap[i++]);
        pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]);
+
+       pci_restore_aspm_l1ss_state(dev);
+
+       /* Restore ASPM control after restoring L1SS state */
+       pcie_capability_set_word(dev, PCI_EXP_LNKCTL,
+                                lnkctl & PCI_EXP_LNKCTL_ASPMC);
 }
 
 static int pci_save_pcix_state(struct pci_dev *dev)

diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
index ad3add45345c567323d60b581274cb3ea7a5543e..eca5938deb07c295c525794dd8bb2d5c4be769ba 100644 (file)
--- a/drivers/pci/pci.h
+++ b/drivers/pci/pci.h
@@ -571,6 +571,9 @@ int pcie_retrain_link(struct pci_dev *pdev, bool use_lt);
 /* ASPM-related functionality we need even without CONFIG_PCIEASPM */
 void pci_save_ltr_state(struct pci_dev *dev);
 void pci_restore_ltr_state(struct pci_dev *dev);
+void pci_configure_aspm_l1ss(struct pci_dev *dev);
+void pci_save_aspm_l1ss_state(struct pci_dev *dev);
+void pci_restore_aspm_l1ss_state(struct pci_dev *dev);
 
 #ifdef CONFIG_PCIEASPM
 void pcie_aspm_init_link_state(struct pci_dev *pdev);

diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c
index 21731b232fb8e4ab37dbbd61be00f83812edaec5..977eca893b2ae0897704fac99c630398116b716b 100644 (file)
--- a/drivers/pci/pcie/aspm.c
+++ b/drivers/pci/pcie/aspm.c
@@ -64,6 +64,105 @@ void pci_restore_ltr_state(struct pci_dev *dev)
        pci_write_config_dword(dev, ltr + PCI_LTR_MAX_SNOOP_LAT, *cap);
 }
 
+void pci_configure_aspm_l1ss(struct pci_dev *pdev)
+{
+       int rc;
+
+       pdev->l1ss = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS);
+
+       rc = pci_add_ext_cap_save_buffer(pdev, PCI_EXT_CAP_ID_L1SS,
+                                        2 * sizeof(u32));
+       if (rc)
+               pci_err(pdev, "unable to allocate ASPM L1SS save buffer (%pe)\n",
+                       ERR_PTR(rc));
+}
+
+void pci_save_aspm_l1ss_state(struct pci_dev *pdev)
+{
+       struct pci_cap_saved_state *save_state;
+       u16 l1ss = pdev->l1ss;
+       u32 *cap;
+
+       /*
+        * Save L1 substate configuration. The ASPM L0s/L1 configuration
+        * in PCI_EXP_LNKCTL_ASPMC is saved by pci_save_pcie_state().
+        */
+       if (!l1ss)
+               return;
+
+       save_state = pci_find_saved_ext_cap(pdev, PCI_EXT_CAP_ID_L1SS);
+       if (!save_state)
+               return;
+
+       cap = &save_state->cap.data[0];
+       pci_read_config_dword(pdev, l1ss + PCI_L1SS_CTL2, cap++);
+       pci_read_config_dword(pdev, l1ss + PCI_L1SS_CTL1, cap++);
+}
+
+void pci_restore_aspm_l1ss_state(struct pci_dev *pdev)
+{
+       struct pci_cap_saved_state *pl_save_state, *cl_save_state;
+       struct pci_dev *parent = pdev->bus->self;
+       u32 *cap, pl_ctl1, pl_ctl2, pl_l1_2_enable;
+       u32 cl_ctl1, cl_ctl2, cl_l1_2_enable;
+
+       /*
+        * In case BIOS enabled L1.2 when resuming, we need to disable it first
+        * on the downstream component before the upstream. So, don't attempt to
+        * restore either until we are at the downstream component.
+        */
+       if (pcie_downstream_port(pdev) || !parent)
+               return;
+
+       if (!pdev->l1ss || !parent->l1ss)
+               return;
+
+       cl_save_state = pci_find_saved_ext_cap(pdev, PCI_EXT_CAP_ID_L1SS);
+       pl_save_state = pci_find_saved_ext_cap(parent, PCI_EXT_CAP_ID_L1SS);
+       if (!cl_save_state || !pl_save_state)
+               return;
+
+       cap = &cl_save_state->cap.data[0];
+       cl_ctl2 = *cap++;
+       cl_ctl1 = *cap;
+       cap = &pl_save_state->cap.data[0];
+       pl_ctl2 = *cap++;
+       pl_ctl1 = *cap;
+
+       /*
+        * Disable L1.2 on this downstream endpoint device first, followed
+        * by the upstream
+        */
+       pci_clear_and_set_config_dword(pdev, pdev->l1ss + PCI_L1SS_CTL1,
+                                      PCI_L1SS_CTL1_L1_2_MASK, 0);
+       pci_clear_and_set_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1,
+                                      PCI_L1SS_CTL1_L1_2_MASK, 0);
+
+       /*
+        * In addition, Common_Mode_Restore_Time and LTR_L1.2_THRESHOLD
+        * in PCI_L1SS_CTL1 must be programmed *before* setting the L1.2
+        * enable bits, even though they're all in PCI_L1SS_CTL1.
+        */
+       pl_l1_2_enable = pl_ctl1 & PCI_L1SS_CTL1_L1_2_MASK;
+       pl_ctl1 &= ~PCI_L1SS_CTL1_L1_2_MASK;
+       cl_l1_2_enable = cl_ctl1 & PCI_L1SS_CTL1_L1_2_MASK;
+       cl_ctl1 &= ~PCI_L1SS_CTL1_L1_2_MASK;
+
+       /* Write back without enables first (above we cleared them in ctl1) */
+       pci_write_config_dword(parent, parent->l1ss + PCI_L1SS_CTL2, pl_ctl2);
+       pci_write_config_dword(pdev, pdev->l1ss + PCI_L1SS_CTL2, cl_ctl2);
+       pci_write_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1, pl_ctl1);
+       pci_write_config_dword(pdev, pdev->l1ss + PCI_L1SS_CTL1, cl_ctl1);
+
+       /* Then write back the enables */
+       if (pl_l1_2_enable || cl_l1_2_enable) {
+               pci_write_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1,
+                                      pl_ctl1 | pl_l1_2_enable);
+               pci_write_config_dword(pdev, pdev->l1ss + PCI_L1SS_CTL1,
+                                      cl_ctl1 | cl_l1_2_enable);
+       }
+}
+
 #ifdef CONFIG_PCIEASPM
 
 #ifdef MODULE_PARAM_PREFIX
@@ -1005,9 +1104,6 @@ void pci_configure_ltr(struct pci_dev *pdev)
        if (!pci_is_pcie(pdev))
                return;
 
-       /* Read L1 PM substate capabilities */
-       pdev->l1ss = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS);
-
        pcie_capability_read_dword(pdev, PCI_EXP_DEVCAP2, &cap);
        if (!(cap & PCI_EXP_DEVCAP2_LTR))
                return;

diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index b809c0b0e0e57e72c7faaba9a2bfc9f83765453b..1434bf495db3c633d3f89c2fadb1959e2b66d2a9 100644 (file)
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -2259,6 +2259,7 @@ static void pci_configure_device(struct pci_dev *dev)
        pci_configure_extended_tags(dev, NULL);
        pci_configure_relaxed_ordering(dev);
        pci_configure_ltr(dev);
+       pci_configure_aspm_l1ss(dev);
        pci_configure_eetlp_prefix(dev);
        pci_configure_serr(dev);
 

diff --git a/include/linux/pci.h b/include/linux/pci.h
index add9368e6314b9d7038a651af3f8e1b9e08d7ffa..6967ae7b41154e395d96e50a8524a11289559aa9 100644 (file)
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -390,9 +390,9 @@ struct pci_dev {
        unsigned int    d3hot_delay;    /* D3hot->D0 transition time in ms */
        unsigned int    d3cold_delay;   /* D3cold->D0 transition time in ms */
 
+       u16             l1ss;           /* L1SS Capability pointer */
 #ifdef CONFIG_PCIEASPM
        struct pcie_link_state  *link_state;    /* ASPM link state */
-       u16             l1ss;           /* L1SS Capability pointer */
        unsigned int    ltr_path:1;     /* Latency Tolerance Reporting
                                           supported from root to here */
 #endif