MSIOF5_RXD_MARK,
};
+/* - PCIE ------------------------------------------------------------------- */
+static const unsigned int pcie0_clkreq_n_pins[] = {
+ /* PCIE0_CLKREQ_N */
+ RCAR_GP_PIN(4, 21),
+};
+
+static const unsigned int pcie0_clkreq_n_mux[] = {
+ PCIE0_CLKREQ_N_MARK,
+};
+
/* - PWM0_A ------------------------------------------------------------------- */
static const unsigned int pwm0_a_pins[] = {
/* PWM0_A */
SH_PFC_PIN_GROUP(msiof5_txd),
SH_PFC_PIN_GROUP(msiof5_rxd),
+ SH_PFC_PIN_GROUP(pcie0_clkreq_n),
+
SH_PFC_PIN_GROUP(pwm0_a),
SH_PFC_PIN_GROUP(pwm0_b),
SH_PFC_PIN_GROUP(pwm1_a),
"msiof5_rxd",
};
+static const char * const pcie_groups[] = {
+ "pcie0_clkreq_n",
+};
+
static const char * const pwm0_groups[] = {
"pwm0_a",
"pwm0_b",
SH_PFC_FUNCTION(msiof4),
SH_PFC_FUNCTION(msiof5),
+ SH_PFC_FUNCTION(pcie),
+
SH_PFC_FUNCTION(pwm0),
SH_PFC_FUNCTION(pwm1),
SH_PFC_FUNCTION(pwm2),