arm64: dts: ti: k3-j721s2-evm*: Add bootph-* properties
authorManorit Chawdhry <m-chawdhry@ti.com>
Thu, 24 Oct 2024 05:21:05 +0000 (10:51 +0530)
committerVignesh Raghavendra <vigneshr@ti.com>
Mon, 28 Oct 2024 15:17:23 +0000 (20:47 +0530)
Adds bootph-* properties to the leaf nodes to enable bootloaders to
utilise them.

Following adds bootph-* to:
- pmic regulator for enabling AVS Support
- main_uart8, mcu_uart0(DM), wkup_uart0(TIFS) for Traces
- mmc0, mmc1, usb0, ospi0, ospi1 for enabling various bootmodes.

Reviewed-by: Andrew Davis <afd@ti.com>
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
Link: https://lore.kernel.org/r/20241024-b4-upstream-bootph-all-v6-8-2af90e3a4fe7@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi

index c5a0b7cbb14f8866bbb06e337f1242455aeeea4e..e2fc1288ed07664591c2d645dc949f182dd71df7 100644 (file)
                        J721S2_IOPAD(0x0d0, PIN_INPUT, 11) /* (AF26) SPI0_CS1.UART8_RXD */
                        J721S2_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AH27) SPI0_CLK.UART8_TXD */
                >;
+               bootph-all;
        };
 
        main_i2c3_pins_default: main-i2c3-default-pins {
                        J721S2_IOPAD(0x0f0, PIN_INPUT, 0) /* (R22) MMC1_DAT3 */
                        J721S2_IOPAD(0x0e8, PIN_INPUT, 8) /* (AE25) TIMER_IO0.MMC1_SDCD */
                >;
+               bootph-all;
        };
 
        vdd_sd_dv_pins_default: vdd-sd-dv-default-pins {
                pinctrl-single,pins = <
                        J721S2_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AG25) TIMER_IO1.USB0_DRVVBUS */
                >;
+               bootph-all;
        };
 
        main_mcan3_pins_default: main-mcan3-default-pins {
                        J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (D28) WKUP_UART0_RXD */
                        J721S2_WKUP_IOPAD(0x04c, PIN_OUTPUT, 0) /* (D27) WKUP_UART0_TXD */
                >;
+               bootph-all;
        };
 
        mcu_uart0_pins_default: mcu-uart0-default-pins {
                        J721S2_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C24) WKUP_GPIO0_13.MCU_UART0_RXD */
                        J721S2_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (C25) WKUP_GPIO0_12.MCU_UART0_TXD */
                >;
+               bootph-all;
        };
 
        mcu_cpsw_pins_default: mcu-cpsw-default-pins {
                        J721S2_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (B19) MCU_OSPI1_DQS */
                        J721S2_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (B20) MCU_OSPI1_LBCLKO */
                >;
+               bootph-all;
        };
 };
 
        status = "reserved";
        pinctrl-names = "default";
        pinctrl-0 = <&wkup_uart0_pins_default>;
+       bootph-all;
 };
 
 &mcu_uart0 {
        status = "okay";
        pinctrl-names = "default";
        pinctrl-0 = <&mcu_uart0_pins_default>;
+       bootph-all;
 };
 
 &main_uart8 {
        pinctrl-0 = <&main_uart8_pins_default>;
        /* Shared with TFA on this platform */
        power-domains = <&k3_pds 357 TI_SCI_PD_SHARED>;
+       bootph-all;
 };
 
 &main_i2c0 {
        /* eMMC */
        status = "okay";
        non-removable;
+       bootph-all;
        ti,driver-strength-ohm = <50>;
        disable-wp;
 };
        disable-wp;
        vmmc-supply = <&vdd_mmc1>;
        vqmmc-supply = <&vdd_sd_dv>;
+       bootph-all;
 };
 
 &mcu_cpsw {
        status = "okay";
        pinctrl-0 = <&main_usbss0_pins_default>;
        pinctrl-names = "default";
+       bootph-all;
        ti,vbus-divider;
        ti,usb2-only;
 };
 &usb0 {
        dr_mode = "otg";
        maximum-speed = "high-speed";
+       bootph-all;
 };
 
 &ospi1 {
                spi-tx-bus-width = <1>;
                spi-rx-bus-width = <4>;
                spi-max-frequency = <40000000>;
+               bootph-all;
                cdns,tshsl-ns = <60>;
                cdns,tsd2d-ns = <60>;
                cdns,tchsh-ns = <60>;
index 89252e4a5f1bc2472b2464faf2fb727c9eedab4e..b3a0385ed3d86cc6e63fe88a554364325fd7967c 100644 (file)
                        J721S2_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (E18) MCU_OSPI0_DQS */
                        J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E20) MCU_OSPI0_LBCLKO */
                >;
+               bootph-all;
        };
 };
 
                        J721S2_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (H24) WKUP_I2C0_SCL */
                        J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (H27) WKUP_I2C0_SDA */
                >;
+               bootph-pre-ram;
        };
 };
 
                spi-tx-bus-width = <8>;
                spi-rx-bus-width = <8>;
                spi-max-frequency = <25000000>;
+               bootph-all;
                cdns,tshsl-ns = <60>;
                cdns,tsd2d-ns = <60>;
                cdns,tchsh-ns = <60>;