net: sparx5: Fix invalid timestamps
authorAakash Menon <aakash.r.menon@gmail.com>
Tue, 17 Sep 2024 05:18:29 +0000 (22:18 -0700)
committerDavid S. Miller <davem@davemloft.net>
Sun, 22 Sep 2024 18:53:19 +0000 (19:53 +0100)
Bit 270-271 are occasionally unexpectedly set by the hardware. This issue
was observed with 10G SFPs causing huge time errors (> 30ms) in PTP. Only
30 bits are needed for the nanosecond part of the timestamp, clear 2 most
significant bits before extracting timestamp from the internal frame
header.

Fixes: 70dfe25cd866 ("net: sparx5: Update extraction/injection for timestamping")
Signed-off-by: Aakash Menon <aakash.menon@protempis.com>
Reviewed-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/ethernet/microchip/sparx5/sparx5_packet.c

index f3f5fb4204689bd3de47d6771a457bccf650829d..70427643f777c098f0284052a8f04ed6e0aa982f 100644 (file)
@@ -45,8 +45,12 @@ void sparx5_ifh_parse(u32 *ifh, struct frame_info *info)
        fwd = (fwd >> 5);
        info->src_port = FIELD_GET(GENMASK(7, 1), fwd);
 
+       /*
+        * Bit 270-271 are occasionally unexpectedly set by the hardware,
+        * clear bits before extracting timestamp
+        */
        info->timestamp =
-               ((u64)xtr_hdr[2] << 24) |
+               ((u64)(xtr_hdr[2] & GENMASK(5, 0)) << 24) |
                ((u64)xtr_hdr[3] << 16) |
                ((u64)xtr_hdr[4] <<  8) |
                ((u64)xtr_hdr[5] <<  0);