mtd: spi-nor: Enable locking for n25q128a11

As 4bit block protection patchset for some micron models are merged,
n25q128a11 also uses 4 bit Block Protection scheme, so enable locking
for it. Tested it on n25q128a11, the locking functions work well.

Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com>
Reviewed-by: Jungseung Lee <js07.lee@samsung.com>
Tested-by: Shreyas Joshi <shreyasjoshi15@gmail.com>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>

diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-st.c
index 6c034b9718e2c9bb6f02db734e5e66341ed7af2e..02c0b53f60971b039e368c765fa62051398424f0 100644 (file)
--- a/drivers/mtd/spi-nor/micron-st.c
+++ b/drivers/mtd/spi-nor/micron-st.c
@@ -29,7 +29,9 @@ static const struct flash_info st_parts[] = {
        { "n25q064a",    INFO(0x20bb17, 0, 64 * 1024,  128,
                              SECT_4K | SPI_NOR_QUAD_READ) },
        { "n25q128a11",  INFO(0x20bb18, 0, 64 * 1024,  256,
-                             SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
+                             SECT_4K | USE_FSR | SPI_NOR_QUAD_READ |
+                             SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB |
+                             SPI_NOR_4BIT_BP | SPI_NOR_BP3_SR_BIT6) },
        { "n25q128a13",  INFO(0x20ba18, 0, 64 * 1024,  256,
                              SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
        { "mt25ql256a",  INFO6(0x20ba19, 0x104400, 64 * 1024,  512,