arm64: dts: imx8mp: add HDMI display pipeline

This adds the DT nodes for all the peripherals that make up the
HDMI display pipeline.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Adam Ford <aford173@gmail.com>
Tested-by: Marek Vasut <marex@denx.de>
Tested-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
Reviewed-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
Tested-by: Tommaso Merciai <tomm.merciai@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index 18bfa7d9aa7f2fff8d71ac448aff4c4b1de363dd..e3510fef6030052077b25a7c9a70b213fc62d7d6 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -1940,6 +1940,102 @@
                                clock-names = "ipg";
                                power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_IRQSTEER>;
                        };
+
+                       hdmi_pvi: display-bridge@32fc4000 {
+                               compatible = "fsl,imx8mp-hdmi-pvi";
+                               reg = <0x32fc4000 0x1000>;
+                               interrupt-parent = <&irqsteer_hdmi>;
+                               interrupts = <12>;
+                               power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_PVI>;
+                               status = "disabled";
+
+                               ports {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+
+                                       port@0 {
+                                               reg = <0>;
+                                               pvi_from_lcdif3: endpoint {
+                                                       remote-endpoint = <&lcdif3_to_pvi>;
+                                               };
+                                       };
+
+                                       port@1 {
+                                               reg = <1>;
+                                               pvi_to_hdmi_tx: endpoint {
+                                                       remote-endpoint = <&hdmi_tx_from_pvi>;
+                                               };
+                                       };
+                               };
+                       };
+
+                       lcdif3: display-controller@32fc6000 {
+                               compatible = "fsl,imx8mp-lcdif";
+                               reg = <0x32fc6000 0x1000>;
+                               interrupt-parent = <&irqsteer_hdmi>;
+                               interrupts = <8>;
+                               clocks = <&hdmi_tx_phy>,
+                                        <&clk IMX8MP_CLK_HDMI_APB>,
+                                        <&clk IMX8MP_CLK_HDMI_ROOT>;
+                               clock-names = "pix", "axi", "disp_axi";
+                               power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_LCDIF>;
+                               status = "disabled";
+
+                               port {
+                                       lcdif3_to_pvi: endpoint {
+                                               remote-endpoint = <&pvi_from_lcdif3>;
+                                       };
+                               };
+                       };
+
+                       hdmi_tx: hdmi@32fd8000 {
+                               compatible = "fsl,imx8mp-hdmi-tx";
+                               reg = <0x32fd8000 0x7eff>;
+                               interrupt-parent = <&irqsteer_hdmi>;
+                               interrupts = <0>;
+                               clocks = <&clk IMX8MP_CLK_HDMI_APB>,
+                                        <&clk IMX8MP_CLK_HDMI_REF_266M>,
+                                        <&clk IMX8MP_CLK_32K>,
+                                        <&hdmi_tx_phy>;
+                               clock-names = "iahb", "isfr", "cec", "pix";
+                               assigned-clocks = <&clk IMX8MP_CLK_HDMI_REF_266M>;
+                               assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>;
+                               power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_HDMI_TX>;
+                               reg-io-width = <1>;
+                               status = "disabled";
+
+                               ports {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+
+                                       port@0 {
+                                               reg = <0>;
+
+                                               hdmi_tx_from_pvi: endpoint {
+                                                       remote-endpoint = <&pvi_to_hdmi_tx>;
+                                               };
+                                       };
+
+                                       port@1 {
+                                               reg = <1>;
+                                               /* Point endpoint to the HDMI connector */
+                                       };
+                               };
+                       };
+
+                       hdmi_tx_phy: phy@32fdff00 {
+                               compatible = "fsl,imx8mp-hdmi-phy";
+                               reg = <0x32fdff00 0x100>;
+                               clocks = <&clk IMX8MP_CLK_HDMI_APB>,
+                                        <&clk IMX8MP_CLK_HDMI_24M>;
+                               clock-names = "apb", "ref";
+                               assigned-clocks = <&clk IMX8MP_CLK_HDMI_24M>;
+                               assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
+                               power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_HDMI_TX_PHY>;
+                               #clock-cells = <0>;
+                               #phy-cells = <0>;
+                               status = "disabled";
+                       };
                };
 
                pcie: pcie@33800000 {