MIPS: Remove MIPS4K_ICACHE_REFILL_WAR and MIPS_CACHE_SYNC_WAR

Neither MIPS4K_ICACHE_REFILL_WAR nor MIPS_CACHE_SYNC_WAR are implemented,
so removing defines for it won't change anything.

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>

diff --git a/arch/mips/include/asm/mach-cavium-octeon/war.h b/arch/mips/include/asm/mach-cavium-octeon/war.h
index 4bc396d0fdd986188434a76b16d27f0cafba010b..5826fbf4d3a2bb4d8c42b13932e77badac9748c4 100644 (file)
--- a/arch/mips/include/asm/mach-cavium-octeon/war.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/war.h
@@ -11,8 +11,6 @@
 
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
-#define MIPS4K_ICACHE_REFILL_WAR       0
-#define MIPS_CACHE_SYNC_WAR            0
 #define TX49XX_ICACHE_INDEX_INV_WAR    0
 #define ICACHE_REFILLS_WORKAROUND_WAR  0
 #define R10000_LLSC_WAR                        0

diff --git a/arch/mips/include/asm/mach-generic/war.h b/arch/mips/include/asm/mach-generic/war.h
index 4d46a880b8320d638ebe57675f2ed1ecdea6edea..11b1f5e41af048936268645d3bfd07c0c8ae418d 100644 (file)
--- a/arch/mips/include/asm/mach-generic/war.h
+++ b/arch/mips/include/asm/mach-generic/war.h
@@ -10,8 +10,6 @@
 
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
-#define MIPS4K_ICACHE_REFILL_WAR       0
-#define MIPS_CACHE_SYNC_WAR            0
 #define TX49XX_ICACHE_INDEX_INV_WAR    0
 #define ICACHE_REFILLS_WORKAROUND_WAR  0
 #define R10000_LLSC_WAR                        0

diff --git a/arch/mips/include/asm/mach-ip22/war.h b/arch/mips/include/asm/mach-ip22/war.h
index a5a1c41df74e2aa5b971fd061bc6f8ec28bd6c29..e47a7e186ed2785274812724ff86b3cef3d3b938 100644 (file)
--- a/arch/mips/include/asm/mach-ip22/war.h
+++ b/arch/mips/include/asm/mach-ip22/war.h
@@ -10,8 +10,6 @@
 
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
-#define MIPS4K_ICACHE_REFILL_WAR       0
-#define MIPS_CACHE_SYNC_WAR            0
 #define TX49XX_ICACHE_INDEX_INV_WAR    0
 #define ICACHE_REFILLS_WORKAROUND_WAR  0
 #define R10000_LLSC_WAR                        0

diff --git a/arch/mips/include/asm/mach-ip27/war.h b/arch/mips/include/asm/mach-ip27/war.h
index 5891d506cffdf38b4f4202683369ed717efeff98..f3c5cc8ff2bca310c391bcc22cc7156bd227c6bf 100644 (file)
--- a/arch/mips/include/asm/mach-ip27/war.h
+++ b/arch/mips/include/asm/mach-ip27/war.h
@@ -10,8 +10,6 @@
 
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
-#define MIPS4K_ICACHE_REFILL_WAR       0
-#define MIPS_CACHE_SYNC_WAR            0
 #define TX49XX_ICACHE_INDEX_INV_WAR    0
 #define ICACHE_REFILLS_WORKAROUND_WAR  0
 #define R10000_LLSC_WAR                        1

diff --git a/arch/mips/include/asm/mach-ip28/war.h b/arch/mips/include/asm/mach-ip28/war.h
index 346fc567ebb347dfbd8ef1d809f3d52e4066c08d..f867697a179313822859a7eaee084b1af7e87333 100644 (file)
--- a/arch/mips/include/asm/mach-ip28/war.h
+++ b/arch/mips/include/asm/mach-ip28/war.h
@@ -10,8 +10,6 @@
 
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
-#define MIPS4K_ICACHE_REFILL_WAR       0
-#define MIPS_CACHE_SYNC_WAR            0
 #define TX49XX_ICACHE_INDEX_INV_WAR    0
 #define ICACHE_REFILLS_WORKAROUND_WAR  0
 #define R10000_LLSC_WAR                        1

diff --git a/arch/mips/include/asm/mach-ip30/war.h b/arch/mips/include/asm/mach-ip30/war.h
index f887a0a53e183433956459ab87ab60dad06173f1..acda1ee3fb629642062f5d5cfd2ed16b73d4c4e5 100644 (file)
--- a/arch/mips/include/asm/mach-ip30/war.h
+++ b/arch/mips/include/asm/mach-ip30/war.h
@@ -7,8 +7,6 @@
 
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
-#define MIPS4K_ICACHE_REFILL_WAR       0
-#define MIPS_CACHE_SYNC_WAR            0
 #define TX49XX_ICACHE_INDEX_INV_WAR    0
 #define ICACHE_REFILLS_WORKAROUND_WAR  0
 #ifdef CONFIG_CPU_R10000

diff --git a/arch/mips/include/asm/mach-ip32/war.h b/arch/mips/include/asm/mach-ip32/war.h
index 980dbd34355c142b859033f6fcab5aa07bb7d3a1..ca381798f6ab7c2a777aa7ba84e6ba7ee809b324 100644 (file)
--- a/arch/mips/include/asm/mach-ip32/war.h
+++ b/arch/mips/include/asm/mach-ip32/war.h
@@ -10,8 +10,6 @@
 
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
-#define MIPS4K_ICACHE_REFILL_WAR       0
-#define MIPS_CACHE_SYNC_WAR            0
 #define TX49XX_ICACHE_INDEX_INV_WAR    0
 #define ICACHE_REFILLS_WORKAROUND_WAR  1
 #define R10000_LLSC_WAR                        0

diff --git a/arch/mips/include/asm/mach-malta/war.h b/arch/mips/include/asm/mach-malta/war.h
index 29f56803e3e5593a8545ca1a3b44afbb88d10516..d22ca4a3ec7233fa5bf166a0bee4f7b34f8331c5 100644 (file)
--- a/arch/mips/include/asm/mach-malta/war.h
+++ b/arch/mips/include/asm/mach-malta/war.h
@@ -10,8 +10,6 @@
 
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
-#define MIPS4K_ICACHE_REFILL_WAR       1
-#define MIPS_CACHE_SYNC_WAR            1
 #define TX49XX_ICACHE_INDEX_INV_WAR    0
 #define ICACHE_REFILLS_WORKAROUND_WAR  1
 #define R10000_LLSC_WAR                        0

diff --git a/arch/mips/include/asm/mach-rc32434/war.h b/arch/mips/include/asm/mach-rc32434/war.h
index 749787bb6c8e260b25b86153e92f00c3376a1f11..fccf25dcc26f519b172dd4e20cc13d8cf0c99a7e 100644 (file)
--- a/arch/mips/include/asm/mach-rc32434/war.h
+++ b/arch/mips/include/asm/mach-rc32434/war.h
@@ -10,8 +10,6 @@
 
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
-#define MIPS4K_ICACHE_REFILL_WAR       1
-#define MIPS_CACHE_SYNC_WAR            0
 #define TX49XX_ICACHE_INDEX_INV_WAR    0
 #define ICACHE_REFILLS_WORKAROUND_WAR  0
 #define R10000_LLSC_WAR                        0

diff --git a/arch/mips/include/asm/mach-rm/war.h b/arch/mips/include/asm/mach-rm/war.h
index aded634ccb01a611bbb3967b9e8c5e7bb0bb2d75..556e0223e60b252793f1434cd9138e2cefd2433f 100644 (file)
--- a/arch/mips/include/asm/mach-rm/war.h
+++ b/arch/mips/include/asm/mach-rm/war.h
@@ -10,8 +10,6 @@
 
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
-#define MIPS4K_ICACHE_REFILL_WAR       0
-#define MIPS_CACHE_SYNC_WAR            0
 #define TX49XX_ICACHE_INDEX_INV_WAR    0
 #define ICACHE_REFILLS_WORKAROUND_WAR  0
 #define R10000_LLSC_WAR                        0

diff --git a/arch/mips/include/asm/mach-sibyte/war.h b/arch/mips/include/asm/mach-sibyte/war.h
index 78fd2ad4930bcbd2956173fb0e8aebee6ed8e615..0e18f0753407226481430f9ef14160fa96ba647d 100644 (file)
--- a/arch/mips/include/asm/mach-sibyte/war.h
+++ b/arch/mips/include/asm/mach-sibyte/war.h
@@ -24,8 +24,6 @@ extern int sb1250_m3_workaround_needed(void);
 
 #endif
 
-#define MIPS4K_ICACHE_REFILL_WAR       0
-#define MIPS_CACHE_SYNC_WAR            0
 #define TX49XX_ICACHE_INDEX_INV_WAR    0
 #define ICACHE_REFILLS_WORKAROUND_WAR  0
 #define R10000_LLSC_WAR                        0

diff --git a/arch/mips/include/asm/mach-tx49xx/war.h b/arch/mips/include/asm/mach-tx49xx/war.h
index 0b1666e0391a935f4816c6d500f44407a9128c70..7019ddc4c68d87aedddca6bb55b01e9ae1cd739f 100644 (file)
--- a/arch/mips/include/asm/mach-tx49xx/war.h
+++ b/arch/mips/include/asm/mach-tx49xx/war.h
@@ -10,8 +10,6 @@
 
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
-#define MIPS4K_ICACHE_REFILL_WAR       0
-#define MIPS_CACHE_SYNC_WAR            0
 #define TX49XX_ICACHE_INDEX_INV_WAR    1
 #define ICACHE_REFILLS_WORKAROUND_WAR  0
 #define R10000_LLSC_WAR                        0

diff --git a/arch/mips/include/asm/war.h b/arch/mips/include/asm/war.h
index 37092c2c68e16b1eb3b012c66fa98d8591fee8c5..590bf2b16b33801d578968e5e1b773101cdafa0f 100644 (file)
--- a/arch/mips/include/asm/war.h
+++ b/arch/mips/include/asm/war.h
@@ -93,41 +93,6 @@
 #error Check setting of SIBYTE_1956_WAR for your platform
 #endif
 
-/*
- * Fill buffers not flushed on CACHE instructions
- *
- * Hit_Invalidate_I cacheops invalidate an icache line but the refill
- * for that line can get stale data from the fill buffer instead of
- * accessing memory if the previous icache miss was also to that line.
- *
- * Workaround: generate an icache refill from a different line
- *
- * Affects:
- *  MIPS 4K            RTL revision <3.0, PRID revision <4
- */
-#ifndef MIPS4K_ICACHE_REFILL_WAR
-#error Check setting of MIPS4K_ICACHE_REFILL_WAR for your platform
-#endif
-
-/*
- * Missing implicit forced flush of evictions caused by CACHE
- * instruction
- *
- * Evictions caused by a CACHE instructions are not forced on to the
- * bus. The BIU gives higher priority to fetches than to the data from
- * the eviction buffer and no collision detection is performed between
- * fetches and pending data from the eviction buffer.
- *
- * Workaround: Execute a SYNC instruction after the cache instruction
- *
- * Affects:
- *   MIPS 5Kc,5Kf      RTL revision <2.3, PRID revision <8
- *   MIPS 20Kc         RTL revision <4.0, PRID revision <?
- */
-#ifndef MIPS_CACHE_SYNC_WAR
-#error Check setting of MIPS_CACHE_SYNC_WAR for your platform
-#endif
-
 /*
  * From TX49/H2 manual: "If the instruction (i.e. CACHE) is issued for
  * the line which this instruction itself exists, the following