soc: mediatek: mtk-pm-domains: Allow probing vreg supply on two MFGs
authorAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Thu, 23 Jun 2022 12:38:49 +0000 (14:38 +0200)
committerMatthias Brugger <matthias.bgg@gmail.com>
Thu, 7 Jul 2022 10:07:23 +0000 (12:07 +0200)
MediaTek SoCs have multiple MFG power-domains, exclusively used for
the GPU which, in turn, requires external power supplies: make sure
to have the MTK_SCPD_DOMAIN_SUPPLY cap on the two topmost MFGs to
allow voting for regulators on/off upon usage of these power domains.

This also ensures that the SRAM is actually powered and that we're
not relying on the bootloader leaving this supply on when performing
the first (and latter) poweron sequence for these domains' sram.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20220623123850.110225-2-angelogioacchino.delregno@collabora.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
drivers/soc/mediatek/mt8183-pm-domains.h
drivers/soc/mediatek/mt8186-pm-domains.h
drivers/soc/mediatek/mt8192-pm-domains.h
drivers/soc/mediatek/mt8195-pm-domains.h

index 71b8757e552d6e249b212945cdca9840dfcb41a4..99de67fe5de89921dc8b757bd55bb8ade97a0aa1 100644 (file)
@@ -41,6 +41,7 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = {
                .pwr_sta2nd_offs = 0x0184,
                .sram_pdn_bits = 0,
                .sram_pdn_ack_bits = 0,
+               .caps = MTK_SCPD_DOMAIN_SUPPLY,
        },
        [MT8183_POWER_DOMAIN_MFG] = {
                .name = "mfg",
index bf2dd0cdc3a85befbe7168ff3df99f9c0a8caa66..108af61854a38101409c68f1a6576b564524eb94 100644 (file)
@@ -51,7 +51,7 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8186[] = {
                                MT8186_TOP_AXI_PROT_EN_1_CLR,
                                MT8186_TOP_AXI_PROT_EN_1_STA),
                },
-               .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
+               .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_DOMAIN_SUPPLY,
        },
        [MT8186_POWER_DOMAIN_MFG2] = {
                .name = "mfg2",
index 558c4ee4784aecd5e94877859180e183a6b38762..b97b2051920fe0b2f3673063105e84b395825ac3 100644 (file)
@@ -58,6 +58,7 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
                .pwr_sta2nd_offs = 0x0170,
                .sram_pdn_bits = GENMASK(8, 8),
                .sram_pdn_ack_bits = GENMASK(12, 12),
+               .caps = MTK_SCPD_DOMAIN_SUPPLY,
        },
        [MT8192_POWER_DOMAIN_MFG1] = {
                .name = "mfg1",
@@ -85,6 +86,7 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
                                    MT8192_TOP_AXI_PROT_EN_2_CLR,
                                    MT8192_TOP_AXI_PROT_EN_2_STA1),
                },
+               .caps = MTK_SCPD_DOMAIN_SUPPLY,
        },
        [MT8192_POWER_DOMAIN_MFG2] = {
                .name = "mfg2",
index 0529d130b67565c738bd985eb5f40675f6befca0..d7387ea1b9c9188ec977b5523ac146fe2b67871a 100644 (file)
@@ -162,7 +162,7 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = {
                                    MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR,
                                    MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA1),
                },
-               .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
+               .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_DOMAIN_SUPPLY,
        },
        [MT8195_POWER_DOMAIN_MFG2] = {
                .name = "mfg2",