clk: xgene: Fix divider with non-zero shift value
authorLoc Ho <lho@apm.com>
Thu, 19 Nov 2015 19:20:30 +0000 (12:20 -0700)
committerStephen Boyd <sboyd@codeaurora.org>
Fri, 20 Nov 2015 18:49:14 +0000 (10:49 -0800)
The X-Gene clock driver missed the divider shift operation when
set the divider value.

Signed-off-by: Loc Ho <lho@apm.com>
Fixes: 308964caeebc ("clk: Add APM X-Gene SoC clock driver")
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
drivers/clk/clk-xgene.c

index 27c0da29eca3dc6c67496ac45de696911f732955..10224b01b97c5c6206372f36f9f81fa7ed861b56 100644 (file)
@@ -351,7 +351,8 @@ static int xgene_clk_set_rate(struct clk_hw *hw, unsigned long rate,
                /* Set new divider */
                data = xgene_clk_read(pclk->param.divider_reg +
                                pclk->param.reg_divider_offset);
-               data &= ~((1 << pclk->param.reg_divider_width) - 1);
+               data &= ~((1 << pclk->param.reg_divider_width) - 1)
+                               << pclk->param.reg_divider_shift;
                data |= divider;
                xgene_clk_write(data, pclk->param.divider_reg +
                                        pclk->param.reg_divider_offset);