pinctrl: sh-pfc: r8a7794: Remove reserved bits
authorSergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Fri, 28 Apr 2017 17:50:29 +0000 (20:50 +0300)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Tue, 16 May 2017 11:48:24 +0000 (13:48 +0200)
The R8A7794 PFC driver was apparently based on the preliminary revisions
of the user's manual which had some signals and MOD_SEL register fields
described which the recent manual changed to reserved. Of course, these
signals haven't ever been really used, which makes removing them
painless.

While at it, make the large *enum* look better by starting a new line
each time a new row in the IPSR and MOD_SEL register field tables is
started.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
drivers/pinctrl/sh-pfc/pfc-r8a7794.c

index c7803d67da0b25431e84e4518c3b256d9cc4c714..7e3ece7e97dffffcaaa1d457e754126505d313d3 100644 (file)
@@ -105,235 +105,279 @@ enum {
        FN_I2C3_SDA_B, FN_SCIF5_TXD_B, FN_D5, FN_SCIF4_RXD_B, FN_I2C0_SCL_D,
 
        /* IPSR1 */
-       FN_D6, FN_SCIF4_TXD_B, FN_I2C0_SDA_D, FN_D7, FN_IRQ3, FN_TCLK1,
-       FN_PWM6_B, FN_D8, FN_HSCIF2_HRX, FN_I2C1_SCL_B, FN_D9, FN_HSCIF2_HTX,
-       FN_I2C1_SDA_B, FN_D10, FN_HSCIF2_HSCK, FN_SCIF1_SCK_C, FN_IRQ6,
-       FN_PWM5_C, FN_D11, FN_HSCIF2_HCTS_N, FN_SCIF1_RXD_C, FN_I2C1_SCL_D,
-       FN_D12, FN_HSCIF2_HRTS_N, FN_SCIF1_TXD_C, FN_I2C1_SDA_D, FN_D13,
-       FN_SCIFA1_SCK, FN_TANS1, FN_PWM2_C, FN_TCLK2_B, FN_D14, FN_SCIFA1_RXD,
-       FN_I2C5_SCL_B, FN_D15, FN_SCIFA1_TXD, FN_I2C5_SDA_B, FN_A0,
-       FN_SCIFB1_SCK, FN_PWM3_B, FN_A1, FN_SCIFB1_TXD, FN_A3, FN_SCIFB0_SCK,
-       FN_A4, FN_SCIFB0_TXD, FN_A5, FN_SCIFB0_RXD, FN_PWM4_B, FN_TPUTO3_C,
+       FN_D6, FN_SCIF4_TXD_B, FN_I2C0_SDA_D,
+       FN_D7, FN_IRQ3, FN_TCLK1, FN_PWM6_B,
+       FN_D8, FN_HSCIF2_HRX, FN_I2C1_SCL_B,
+       FN_D9, FN_HSCIF2_HTX, FN_I2C1_SDA_B,
+       FN_D10, FN_HSCIF2_HSCK, FN_SCIF1_SCK_C, FN_IRQ6, FN_PWM5_C,
+       FN_D11, FN_HSCIF2_HCTS_N, FN_SCIF1_RXD_C, FN_I2C1_SCL_D,
+       FN_D12, FN_HSCIF2_HRTS_N, FN_SCIF1_TXD_C, FN_I2C1_SDA_D,
+       FN_D13, FN_SCIFA1_SCK, FN_PWM2_C, FN_TCLK2_B,
+       FN_D14, FN_SCIFA1_RXD, FN_I2C5_SCL_B,
+       FN_D15, FN_SCIFA1_TXD, FN_I2C5_SDA_B,
+       FN_A0, FN_SCIFB1_SCK, FN_PWM3_B,
+       FN_A1, FN_SCIFB1_TXD,
+       FN_A3, FN_SCIFB0_SCK,
+       FN_A4, FN_SCIFB0_TXD,
+       FN_A5, FN_SCIFB0_RXD, FN_PWM4_B, FN_TPUTO3_C,
        FN_A6, FN_SCIFB0_CTS_N, FN_SCIFA4_RXD_B, FN_TPUTO2_C,
 
        /* IPSR2 */
-       FN_A7, FN_SCIFB0_RTS_N, FN_SCIFA4_TXD_B, FN_A8, FN_MSIOF1_RXD,
-       FN_SCIFA0_RXD_B, FN_A9, FN_MSIOF1_TXD, FN_SCIFA0_TXD_B, FN_A10,
-       FN_MSIOF1_SCK, FN_IIC0_SCL_B, FN_A11, FN_MSIOF1_SYNC, FN_IIC0_SDA_B,
-       FN_A12, FN_MSIOF1_SS1, FN_SCIFA5_RXD_B, FN_A13, FN_MSIOF1_SS2,
-       FN_SCIFA5_TXD_B, FN_A14, FN_MSIOF2_RXD, FN_HSCIF0_HRX_B, FN_DREQ1_N,
-       FN_A15, FN_MSIOF2_TXD, FN_HSCIF0_HTX_B, FN_DACK1, FN_A16,
-       FN_MSIOF2_SCK, FN_HSCIF0_HSCK_B, FN_SPEEDIN, FN_VSP, FN_CAN_CLK_C,
-       FN_TPUTO2_B, FN_A17, FN_MSIOF2_SYNC, FN_SCIF4_RXD_E, FN_CAN1_RX_B,
-       FN_AVB_AVTP_CAPTURE_B, FN_A18, FN_MSIOF2_SS1, FN_SCIF4_TXD_E,
-       FN_CAN1_TX_B, FN_AVB_AVTP_MATCH_B, FN_A19, FN_MSIOF2_SS2, FN_PWM4,
-       FN_TPUTO2, FN_MOUT0, FN_A20, FN_SPCLK, FN_MOUT1,
+       FN_A7, FN_SCIFB0_RTS_N, FN_SCIFA4_TXD_B,
+       FN_A8, FN_MSIOF1_RXD, FN_SCIFA0_RXD_B,
+       FN_A9, FN_MSIOF1_TXD, FN_SCIFA0_TXD_B,
+       FN_A10, FN_MSIOF1_SCK, FN_IIC0_SCL_B,
+       FN_A11, FN_MSIOF1_SYNC, FN_IIC0_SDA_B,
+       FN_A12, FN_MSIOF1_SS1, FN_SCIFA5_RXD_B,
+       FN_A13, FN_MSIOF1_SS2, FN_SCIFA5_TXD_B,
+       FN_A14, FN_MSIOF2_RXD, FN_HSCIF0_HRX_B, FN_DREQ1_N,
+       FN_A15, FN_MSIOF2_TXD, FN_HSCIF0_HTX_B, FN_DACK1,
+       FN_A16, FN_MSIOF2_SCK, FN_HSCIF0_HSCK_B, FN_SPEEDIN, FN_CAN_CLK_C,
+       FN_TPUTO2_B,
+       FN_A17, FN_MSIOF2_SYNC, FN_SCIF4_RXD_E, FN_CAN1_RX_B,
+       FN_A18, FN_MSIOF2_SS1, FN_SCIF4_TXD_E, FN_CAN1_TX_B,
+       FN_A19, FN_MSIOF2_SS2, FN_PWM4, FN_TPUTO2,
+       FN_A20, FN_SPCLK,
 
        /* IPSR3 */
-       FN_A21, FN_MOSI_IO0, FN_MOUT2, FN_A22, FN_MISO_IO1, FN_MOUT5,
-       FN_ATADIR1_N, FN_A23, FN_IO2, FN_MOUT6, FN_ATAWR1_N, FN_A24, FN_IO3,
-       FN_EX_WAIT2, FN_A25, FN_SSL, FN_ATARD1_N, FN_CS0_N, FN_VI1_DATA8,
-       FN_CS1_N_A26, FN_VI1_DATA9, FN_EX_CS0_N, FN_VI1_DATA10, FN_EX_CS1_N,
-       FN_TPUTO3_B, FN_SCIFB2_RXD, FN_VI1_DATA11, FN_EX_CS2_N, FN_PWM0,
-       FN_SCIF4_RXD_C, FN_TS_SDATA_B, FN_RIF0_SYNC, FN_TPUTO3, FN_SCIFB2_TXD,
-       FN_SDATA_B, FN_EX_CS3_N, FN_SCIFA2_SCK, FN_SCIF4_TXD_C, FN_TS_SCK_B,
-       FN_RIF0_CLK, FN_BPFCLK, FN_SCIFB2_SCK, FN_MDATA_B, FN_EX_CS4_N,
-       FN_SCIFA2_RXD, FN_I2C2_SCL_E, FN_TS_SDEN_B, FN_RIF0_D0, FN_FMCLK,
-       FN_SCIFB2_CTS_N, FN_SCKZ_B, FN_EX_CS5_N, FN_SCIFA2_TXD, FN_I2C2_SDA_E,
-       FN_TS_SPSYNC_B, FN_RIF0_D1, FN_FMIN, FN_SCIFB2_RTS_N, FN_STM_N_B,
-       FN_BS_N, FN_DRACK0, FN_PWM1_C, FN_TPUTO0_C, FN_ATACS01_N, FN_MTS_N_B,
-       FN_RD_N, FN_ATACS11_N, FN_RD_WR_N, FN_ATAG1_N,
+       FN_A21, FN_MOSI_IO0,
+       FN_A22, FN_MISO_IO1, FN_ATADIR1_N,
+       FN_A23, FN_IO2, FN_ATAWR1_N,
+       FN_A24, FN_IO3, FN_EX_WAIT2,
+       FN_A25, FN_SSL, FN_ATARD1_N,
+       FN_CS0_N, FN_VI1_DATA8,
+       FN_CS1_N_A26, FN_VI1_DATA9,
+       FN_EX_CS0_N, FN_VI1_DATA10,
+       FN_EX_CS1_N, FN_TPUTO3_B, FN_SCIFB2_RXD, FN_VI1_DATA11,
+       FN_EX_CS2_N, FN_PWM0, FN_SCIF4_RXD_C, FN_TS_SDATA_B, FN_TPUTO3,
+       FN_SCIFB2_TXD,
+       FN_EX_CS3_N, FN_SCIFA2_SCK, FN_SCIF4_TXD_C, FN_TS_SCK_B, FN_BPFCLK,
+       FN_SCIFB2_SCK,
+       FN_EX_CS4_N, FN_SCIFA2_RXD, FN_I2C2_SCL_E, FN_TS_SDEN_B, FN_FMCLK,
+       FN_SCIFB2_CTS_N,
+       FN_EX_CS5_N, FN_SCIFA2_TXD, FN_I2C2_SDA_E, FN_TS_SPSYNC_B, FN_FMIN,
+       FN_SCIFB2_RTS_N,
+       FN_BS_N, FN_DRACK0, FN_PWM1_C, FN_TPUTO0_C, FN_ATACS01_N,
+       FN_RD_N, FN_ATACS11_N,
+       FN_RD_WR_N, FN_ATAG1_N,
 
        /* IPSR4 */
-       FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK, FN_PWMFSW0, FN_DU0_DR0,
-       FN_LCDOUT16, FN_SCIF5_RXD_C, FN_I2C2_SCL_D, FN_CC50_STATE0,
-       FN_DU0_DR1, FN_LCDOUT17, FN_SCIF5_TXD_C, FN_I2C2_SDA_D, FN_CC50_STATE1,
-       FN_DU0_DR2, FN_LCDOUT18, FN_CC50_STATE2, FN_DU0_DR3, FN_LCDOUT19,
-       FN_CC50_STATE3, FN_DU0_DR4, FN_LCDOUT20, FN_CC50_STATE4, FN_DU0_DR5,
-       FN_LCDOUT21, FN_CC50_STATE5, FN_DU0_DR6, FN_LCDOUT22, FN_CC50_STATE6,
-       FN_DU0_DR7, FN_LCDOUT23, FN_CC50_STATE7, FN_DU0_DG0, FN_LCDOUT8,
-       FN_SCIFA0_RXD_C, FN_I2C3_SCL_D, FN_CC50_STATE8, FN_DU0_DG1, FN_LCDOUT9,
-       FN_SCIFA0_TXD_C, FN_I2C3_SDA_D, FN_CC50_STATE9, FN_DU0_DG2, FN_LCDOUT10,
-       FN_CC50_STATE10, FN_DU0_DG3, FN_LCDOUT11, FN_CC50_STATE11, FN_DU0_DG4,
-       FN_LCDOUT12, FN_CC50_STATE12,
+       FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK,
+       FN_DU0_DR0, FN_LCDOUT16, FN_SCIF5_RXD_C, FN_I2C2_SCL_D,
+       FN_DU0_DR1, FN_LCDOUT17, FN_SCIF5_TXD_C, FN_I2C2_SDA_D,
+       FN_DU0_DR2, FN_LCDOUT18,
+       FN_DU0_DR3, FN_LCDOUT19,
+       FN_DU0_DR4, FN_LCDOUT20,
+       FN_DU0_DR5, FN_LCDOUT21,
+       FN_DU0_DR6, FN_LCDOUT22,
+       FN_DU0_DR7, FN_LCDOUT23,
+       FN_DU0_DG0, FN_LCDOUT8, FN_SCIFA0_RXD_C, FN_I2C3_SCL_D,
+       FN_DU0_DG1, FN_LCDOUT9, FN_SCIFA0_TXD_C, FN_I2C3_SDA_D,
+       FN_DU0_DG2, FN_LCDOUT10,
+       FN_DU0_DG3, FN_LCDOUT11,
+       FN_DU0_DG4, FN_LCDOUT12,
 
        /* IPSR5 */
-       FN_DU0_DG5, FN_LCDOUT13, FN_CC50_STATE13, FN_DU0_DG6, FN_LCDOUT14,
-       FN_CC50_STATE14, FN_DU0_DG7, FN_LCDOUT15, FN_CC50_STATE15, FN_DU0_DB0,
-       FN_LCDOUT0, FN_SCIFA4_RXD_C, FN_I2C4_SCL_D, FN_CAN0_RX_C,
-       FN_CC50_STATE16, FN_DU0_DB1, FN_LCDOUT1, FN_SCIFA4_TXD_C, FN_I2C4_SDA_D,
-       FN_CAN0_TX_C, FN_CC50_STATE17, FN_DU0_DB2, FN_LCDOUT2, FN_CC50_STATE18,
-       FN_DU0_DB3, FN_LCDOUT3, FN_CC50_STATE19, FN_DU0_DB4, FN_LCDOUT4,
-       FN_CC50_STATE20, FN_DU0_DB5, FN_LCDOUT5, FN_CC50_STATE21, FN_DU0_DB6,
-       FN_LCDOUT6, FN_CC50_STATE22, FN_DU0_DB7, FN_LCDOUT7, FN_CC50_STATE23,
-       FN_DU0_DOTCLKIN, FN_QSTVA_QVS, FN_CC50_STATE24, FN_DU0_DOTCLKOUT0,
-       FN_QCLK, FN_CC50_STATE25, FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE,
-       FN_CC50_STATE26, FN_DU0_EXHSYNC_DU0_HSYNC, FN_QSTH_QHS, FN_CC50_STATE27,
+       FN_DU0_DG5, FN_LCDOUT13,
+       FN_DU0_DG6, FN_LCDOUT14,
+       FN_DU0_DG7, FN_LCDOUT15,
+       FN_DU0_DB0, FN_LCDOUT0, FN_SCIFA4_RXD_C, FN_I2C4_SCL_D, FN_CAN0_RX_C,
+       FN_DU0_DB1, FN_LCDOUT1, FN_SCIFA4_TXD_C, FN_I2C4_SDA_D, FN_CAN0_TX_C,
+       FN_DU0_DB2, FN_LCDOUT2,
+       FN_DU0_DB3, FN_LCDOUT3,
+       FN_DU0_DB4, FN_LCDOUT4,
+       FN_DU0_DB5, FN_LCDOUT5,
+       FN_DU0_DB6, FN_LCDOUT6,
+       FN_DU0_DB7, FN_LCDOUT7,
+       FN_DU0_DOTCLKIN, FN_QSTVA_QVS,
+       FN_DU0_DOTCLKOUT0, FN_QCLK,
+       FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE,
+       FN_DU0_EXHSYNC_DU0_HSYNC, FN_QSTH_QHS,
 
        /* IPSR6 */
-       FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, FN_CC50_STATE28,
-       FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, FN_CC50_STATE29,
-       FN_DU0_DISP, FN_QPOLA, FN_CC50_STATE30, FN_DU0_CDE, FN_QPOLB,
-       FN_CC50_STATE31, FN_VI0_CLK, FN_AVB_RX_CLK, FN_VI0_DATA0_VI0_B0,
-       FN_AVB_RX_DV, FN_VI0_DATA1_VI0_B1, FN_AVB_RXD0, FN_VI0_DATA2_VI0_B2,
-       FN_AVB_RXD1, FN_VI0_DATA3_VI0_B3, FN_AVB_RXD2, FN_VI0_DATA4_VI0_B4,
-       FN_AVB_RXD3, FN_VI0_DATA5_VI0_B5, FN_AVB_RXD4, FN_VI0_DATA6_VI0_B6,
-       FN_AVB_RXD5, FN_VI0_DATA7_VI0_B7, FN_AVB_RXD6, FN_VI0_CLKENB,
-       FN_I2C3_SCL, FN_SCIFA5_RXD_C, FN_IETX_C, FN_AVB_RXD7, FN_VI0_FIELD,
-       FN_I2C3_SDA, FN_SCIFA5_TXD_C, FN_IECLK_C, FN_AVB_RX_ER, FN_VI0_HSYNC_N,
-       FN_SCIF0_RXD_B, FN_I2C0_SCL_C, FN_IERX_C, FN_AVB_COL, FN_VI0_VSYNC_N,
-       FN_SCIF0_TXD_B, FN_I2C0_SDA_C, FN_AUDIO_CLKOUT_B, FN_AVB_TX_EN,
+       FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE,
+       FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE,
+       FN_DU0_DISP, FN_QPOLA,
+       FN_DU0_CDE, FN_QPOLB,
+       FN_VI0_CLK, FN_AVB_RX_CLK,
+       FN_VI0_DATA0_VI0_B0, FN_AVB_RX_DV,
+       FN_VI0_DATA1_VI0_B1, FN_AVB_RXD0,
+       FN_VI0_DATA2_VI0_B2, FN_AVB_RXD1,
+       FN_VI0_DATA3_VI0_B3, FN_AVB_RXD2,
+       FN_VI0_DATA4_VI0_B4, FN_AVB_RXD3,
+       FN_VI0_DATA5_VI0_B5, FN_AVB_RXD4,
+       FN_VI0_DATA6_VI0_B6, FN_AVB_RXD5,
+       FN_VI0_DATA7_VI0_B7, FN_AVB_RXD6,
+       FN_VI0_CLKENB, FN_I2C3_SCL, FN_SCIFA5_RXD_C, FN_IETX_C, FN_AVB_RXD7,
+       FN_VI0_FIELD, FN_I2C3_SDA, FN_SCIFA5_TXD_C, FN_IECLK_C, FN_AVB_RX_ER,
+       FN_VI0_HSYNC_N, FN_SCIF0_RXD_B, FN_I2C0_SCL_C, FN_IERX_C, FN_AVB_COL,
+       FN_VI0_VSYNC_N, FN_SCIF0_TXD_B, FN_I2C0_SDA_C, FN_AUDIO_CLKOUT_B,
+       FN_AVB_TX_EN,
        FN_ETH_MDIO, FN_VI0_G0, FN_MSIOF2_RXD_B, FN_I2C5_SCL_D, FN_AVB_TX_CLK,
-       FN_ADIDATA, FN_AD_DI,
+       FN_ADIDATA,
 
        /* IPSR7 */
        FN_ETH_CRS_DV, FN_VI0_G1, FN_MSIOF2_TXD_B, FN_I2C5_SDA_D, FN_AVB_TXD0,
-       FN_ADICS_SAMP, FN_AD_DO, FN_ETH_RX_ER, FN_VI0_G2, FN_MSIOF2_SCK_B,
-       FN_CAN0_RX_B, FN_AVB_TXD1, FN_ADICLK, FN_AD_CLK, FN_ETH_RXD0, FN_VI0_G3,
-       FN_MSIOF2_SYNC_B, FN_CAN0_TX_B, FN_AVB_TXD2, FN_ADICHS0, FN_AD_NCS_N,
+       FN_ADICS_SAMP,
+       FN_ETH_RX_ER, FN_VI0_G2, FN_MSIOF2_SCK_B, FN_CAN0_RX_B, FN_AVB_TXD1,
+       FN_ADICLK,
+       FN_ETH_RXD0, FN_VI0_G3, FN_MSIOF2_SYNC_B, FN_CAN0_TX_B, FN_AVB_TXD2,
+       FN_ADICHS0,
        FN_ETH_RXD1, FN_VI0_G4, FN_MSIOF2_SS1_B, FN_SCIF4_RXD_D, FN_AVB_TXD3,
-       FN_ADICHS1, FN_ETH_LINK, FN_VI0_G5, FN_MSIOF2_SS2_B, FN_SCIF4_TXD_D,
-       FN_AVB_TXD4, FN_ADICHS2, FN_ETH_REFCLK, FN_VI0_G6, FN_SCIF2_SCK_C,
-       FN_AVB_TXD5, FN_SSI_SCK5_B, FN_ETH_TXD1, FN_VI0_G7, FN_SCIF2_RXD_C,
-       FN_IIC0_SCL_D, FN_AVB_TXD6, FN_SSI_WS5_B, FN_ETH_TX_EN, FN_VI0_R0,
-       FN_SCIF2_TXD_C, FN_IIC0_SDA_D, FN_AVB_TXD7, FN_SSI_SDATA5_B,
+       FN_ADICHS1,
+       FN_ETH_LINK, FN_VI0_G5, FN_MSIOF2_SS2_B, FN_SCIF4_TXD_D, FN_AVB_TXD4,
+       FN_ADICHS2,
+       FN_ETH_REFCLK, FN_VI0_G6, FN_SCIF2_SCK_C, FN_AVB_TXD5, FN_SSI_SCK5_B,
+       FN_ETH_TXD1, FN_VI0_G7, FN_SCIF2_RXD_C, FN_IIC0_SCL_D, FN_AVB_TXD6,
+       FN_SSI_WS5_B,
+       FN_ETH_TX_EN, FN_VI0_R0, FN_SCIF2_TXD_C, FN_IIC0_SDA_D, FN_AVB_TXD7,
+       FN_SSI_SDATA5_B,
        FN_ETH_MAGIC, FN_VI0_R1, FN_SCIF3_SCK_B, FN_AVB_TX_ER, FN_SSI_SCK6_B,
        FN_ETH_TXD0, FN_VI0_R2, FN_SCIF3_RXD_B, FN_I2C4_SCL_E, FN_AVB_GTX_CLK,
-       FN_SSI_WS6_B, FN_DREQ0_N, FN_SCIFB1_RXD,
+       FN_SSI_WS6_B,
+       FN_DREQ0_N, FN_SCIFB1_RXD,
 
        /* IPSR8 */
        FN_ETH_MDC, FN_VI0_R3, FN_SCIF3_TXD_B, FN_I2C4_SDA_E, FN_AVB_MDC,
-       FN_SSI_SDATA6_B, FN_HSCIF0_HRX, FN_VI0_R4, FN_I2C1_SCL_C,
-       FN_AUDIO_CLKA_B, FN_AVB_MDIO, FN_SSI_SCK78_B, FN_HSCIF0_HTX,
-       FN_VI0_R5, FN_I2C1_SDA_C, FN_AUDIO_CLKB_B, FN_AVB_LINK, FN_SSI_WS78_B,
+       FN_SSI_SDATA6_B,
+       FN_HSCIF0_HRX, FN_VI0_R4, FN_I2C1_SCL_C, FN_AUDIO_CLKA_B, FN_AVB_MDIO,
+       FN_SSI_SCK78_B,
+       FN_HSCIF0_HTX, FN_VI0_R5, FN_I2C1_SDA_C, FN_AUDIO_CLKB_B, FN_AVB_LINK,
+       FN_SSI_WS78_B,
        FN_HSCIF0_HCTS_N, FN_VI0_R6, FN_SCIF0_RXD_D, FN_I2C0_SCL_E,
-       FN_AVB_MAGIC, FN_SSI_SDATA7_B, FN_HSCIF0_HRTS_N, FN_VI0_R7,
-       FN_SCIF0_TXD_D, FN_I2C0_SDA_E, FN_AVB_PHY_INT, FN_SSI_SDATA8_B,
+       FN_AVB_MAGIC, FN_SSI_SDATA7_B,
+       FN_HSCIF0_HRTS_N, FN_VI0_R7, FN_SCIF0_TXD_D, FN_I2C0_SDA_E,
+       FN_AVB_PHY_INT, FN_SSI_SDATA8_B,
        FN_HSCIF0_HSCK, FN_SCIF_CLK_B, FN_AVB_CRS, FN_AUDIO_CLKC_B,
        FN_I2C0_SCL, FN_SCIF0_RXD_C, FN_PWM5, FN_TCLK1_B, FN_AVB_GTXREFCLK,
-       FN_CAN1_RX_D, FN_TPUTO0_B, FN_I2C0_SDA, FN_SCIF0_TXD_C, FN_TPUTO0,
-       FN_CAN_CLK, FN_DVC_MUTE, FN_CAN1_TX_D, FN_I2C1_SCL, FN_SCIF4_RXD,
-       FN_PWM5_B, FN_DU1_DR0, FN_RIF1_SYNC_B, FN_TS_SDATA_D, FN_TPUTO1_B,
-       FN_I2C1_SDA, FN_SCIF4_TXD, FN_IRQ5, FN_DU1_DR1, FN_RIF1_CLK_B,
-       FN_TS_SCK_D, FN_BPFCLK_C, FN_MSIOF0_RXD, FN_SCIF5_RXD, FN_I2C2_SCL_C,
-       FN_DU1_DR2, FN_RIF1_D0_B, FN_TS_SDEN_D, FN_FMCLK_C, FN_RDS_CLK,
+       FN_CAN1_RX_D, FN_TPUTO0_B,
+       FN_I2C0_SDA, FN_SCIF0_TXD_C, FN_TPUTO0, FN_CAN_CLK, FN_DVC_MUTE,
+       FN_CAN1_TX_D,
+       FN_I2C1_SCL, FN_SCIF4_RXD, FN_PWM5_B, FN_DU1_DR0, FN_TS_SDATA_D,
+       FN_TPUTO1_B,
+       FN_I2C1_SDA, FN_SCIF4_TXD, FN_IRQ5, FN_DU1_DR1, FN_TS_SCK_D,
+       FN_BPFCLK_C,
+       FN_MSIOF0_RXD, FN_SCIF5_RXD, FN_I2C2_SCL_C, FN_DU1_DR2, FN_TS_SDEN_D,
+       FN_FMCLK_C,
 
        /* IPSR9 */
-       FN_MSIOF0_TXD, FN_SCIF5_TXD, FN_I2C2_SDA_C, FN_DU1_DR3, FN_RIF1_D1_B,
-       FN_TS_SPSYNC_D, FN_FMIN_C, FN_RDS_DATA, FN_MSIOF0_SCK, FN_IRQ0,
-       FN_TS_SDATA, FN_DU1_DR4, FN_RIF1_SYNC, FN_TPUTO1_C, FN_MSIOF0_SYNC,
-       FN_PWM1, FN_TS_SCK, FN_DU1_DR5, FN_RIF1_CLK, FN_BPFCLK_B, FN_MSIOF0_SS1,
-       FN_SCIFA0_RXD, FN_TS_SDEN, FN_DU1_DR6, FN_RIF1_D0, FN_FMCLK_B,
-       FN_RDS_CLK_B, FN_MSIOF0_SS2, FN_SCIFA0_TXD, FN_TS_SPSYNC, FN_DU1_DR7,
-       FN_RIF1_D1, FN_FMIN_B, FN_RDS_DATA_B, FN_HSCIF1_HRX, FN_I2C4_SCL,
-       FN_PWM6, FN_DU1_DG0, FN_HSCIF1_HTX, FN_I2C4_SDA, FN_TPUTO1, FN_DU1_DG1,
+       FN_MSIOF0_TXD, FN_SCIF5_TXD, FN_I2C2_SDA_C, FN_DU1_DR3, FN_TS_SPSYNC_D,
+       FN_FMIN_C,
+       FN_MSIOF0_SCK, FN_IRQ0, FN_TS_SDATA, FN_DU1_DR4, FN_TPUTO1_C,
+       FN_MSIOF0_SYNC, FN_PWM1, FN_TS_SCK, FN_DU1_DR5, FN_BPFCLK_B,
+       FN_MSIOF0_SS1, FN_SCIFA0_RXD, FN_TS_SDEN, FN_DU1_DR6, FN_FMCLK_B,
+       FN_MSIOF0_SS2, FN_SCIFA0_TXD, FN_TS_SPSYNC, FN_DU1_DR7, FN_FMIN_B,
+       FN_HSCIF1_HRX, FN_I2C4_SCL, FN_PWM6, FN_DU1_DG0,
+       FN_HSCIF1_HTX, FN_I2C4_SDA, FN_TPUTO1, FN_DU1_DG1,
        FN_HSCIF1_HSCK, FN_PWM2, FN_IETX, FN_DU1_DG2, FN_REMOCON_B,
-       FN_SPEEDIN_B, FN_VSP_B, FN_HSCIF1_HCTS_N, FN_SCIFA4_RXD, FN_IECLK,
-       FN_DU1_DG3, FN_SSI_SCK1_B, FN_CAN_DEBUG_HW_TRIGGER, FN_CC50_STATE32,
+       FN_SPEEDIN_B,
+       FN_HSCIF1_HCTS_N, FN_SCIFA4_RXD, FN_IECLK, FN_DU1_DG3, FN_SSI_SCK1_B,
        FN_HSCIF1_HRTS_N, FN_SCIFA4_TXD, FN_IERX, FN_DU1_DG4, FN_SSI_WS1_B,
-       FN_CAN_STEP0, FN_CC50_STATE33, FN_SCIF1_SCK, FN_PWM3, FN_TCLK2,
-       FN_DU1_DG5, FN_SSI_SDATA1_B, FN_CAN_TXCLK, FN_CC50_STATE34,
+       FN_SCIF1_SCK, FN_PWM3, FN_TCLK2, FN_DU1_DG5, FN_SSI_SDATA1_B,
 
        /* IPSR10 */
-       FN_SCIF1_RXD, FN_I2C5_SCL, FN_DU1_DG6, FN_SSI_SCK2_B, FN_CAN_DEBUGOUT0,
-       FN_CC50_STATE35, FN_SCIF1_TXD, FN_I2C5_SDA, FN_DU1_DG7, FN_SSI_WS2_B,
-       FN_CAN_DEBUGOUT1, FN_CC50_STATE36, FN_SCIF2_RXD, FN_IIC0_SCL,
-       FN_DU1_DB0, FN_SSI_SDATA2_B, FN_USB0_EXTLP, FN_CAN_DEBUGOUT2,
-       FN_CC50_STATE37, FN_SCIF2_TXD, FN_IIC0_SDA, FN_DU1_DB1, FN_SSI_SCK9_B,
-       FN_USB0_OVC1, FN_CAN_DEBUGOUT3, FN_CC50_STATE38, FN_SCIF2_SCK, FN_IRQ1,
-       FN_DU1_DB2, FN_SSI_WS9_B, FN_USB0_IDIN, FN_CAN_DEBUGOUT4,
-       FN_CC50_STATE39, FN_SCIF3_SCK, FN_IRQ2, FN_BPFCLK_D, FN_DU1_DB3,
-       FN_SSI_SDATA9_B, FN_TANS2, FN_CAN_DEBUGOUT5, FN_CC50_OSCOUT,
+       FN_SCIF1_RXD, FN_I2C5_SCL, FN_DU1_DG6, FN_SSI_SCK2_B,
+       FN_SCIF1_TXD, FN_I2C5_SDA, FN_DU1_DG7, FN_SSI_WS2_B,
+       FN_SCIF2_RXD, FN_IIC0_SCL, FN_DU1_DB0, FN_SSI_SDATA2_B,
+       FN_SCIF2_TXD, FN_IIC0_SDA, FN_DU1_DB1, FN_SSI_SCK9_B,
+       FN_SCIF2_SCK, FN_IRQ1, FN_DU1_DB2, FN_SSI_WS9_B,
+       FN_SCIF3_SCK, FN_IRQ2, FN_BPFCLK_D, FN_DU1_DB3, FN_SSI_SDATA9_B,
        FN_SCIF3_RXD, FN_I2C1_SCL_E, FN_FMCLK_D, FN_DU1_DB4, FN_AUDIO_CLKA_C,
-       FN_SSI_SCK4_B, FN_CAN_DEBUGOUT6, FN_RDS_CLK_C, FN_SCIF3_TXD,
-       FN_I2C1_SDA_E, FN_FMIN_D, FN_DU1_DB5, FN_AUDIO_CLKB_C, FN_SSI_WS4_B,
-       FN_CAN_DEBUGOUT7, FN_RDS_DATA_C, FN_I2C2_SCL, FN_SCIFA5_RXD, FN_DU1_DB6,
-       FN_AUDIO_CLKC_C, FN_SSI_SDATA4_B, FN_CAN_DEBUGOUT8, FN_I2C2_SDA,
-       FN_SCIFA5_TXD, FN_DU1_DB7, FN_AUDIO_CLKOUT_C, FN_CAN_DEBUGOUT9,
-       FN_SSI_SCK5, FN_SCIFA3_SCK, FN_DU1_DOTCLKIN, FN_CAN_DEBUGOUT10,
+       FN_SSI_SCK4_B,
+       FN_SCIF3_TXD, FN_I2C1_SDA_E, FN_FMIN_D, FN_DU1_DB5, FN_AUDIO_CLKB_C,
+       FN_SSI_WS4_B,
+       FN_I2C2_SCL, FN_SCIFA5_RXD, FN_DU1_DB6, FN_AUDIO_CLKC_C,
+       FN_SSI_SDATA4_B,
+       FN_I2C2_SDA, FN_SCIFA5_TXD, FN_DU1_DB7, FN_AUDIO_CLKOUT_C,
+       FN_SSI_SCK5, FN_SCIFA3_SCK, FN_DU1_DOTCLKIN,
 
        /* IPSR11 */
        FN_SSI_WS5, FN_SCIFA3_RXD, FN_I2C3_SCL_C, FN_DU1_DOTCLKOUT0,
-       FN_CAN_DEBUGOUT11, FN_SSI_SDATA5, FN_SCIFA3_TXD, FN_I2C3_SDA_C,
-       FN_DU1_DOTCLKOUT1, FN_CAN_DEBUGOUT12, FN_SSI_SCK6, FN_SCIFA1_SCK_B,
-       FN_DU1_EXHSYNC_DU1_HSYNC, FN_CAN_DEBUGOUT13, FN_SSI_WS6,
-       FN_SCIFA1_RXD_B, FN_I2C4_SCL_C, FN_DU1_EXVSYNC_DU1_VSYNC,
-       FN_CAN_DEBUGOUT14, FN_SSI_SDATA6, FN_SCIFA1_TXD_B, FN_I2C4_SDA_C,
-       FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_CAN_DEBUGOUT15, FN_SSI_SCK78,
-       FN_SCIFA2_SCK_B, FN_I2C5_SDA_C, FN_DU1_DISP, FN_SSI_WS78,
-       FN_SCIFA2_RXD_B, FN_I2C5_SCL_C, FN_DU1_CDE, FN_SSI_SDATA7,
-       FN_SCIFA2_TXD_B, FN_IRQ8, FN_AUDIO_CLKA_D, FN_CAN_CLK_D, FN_PCMOE_N,
+       FN_SSI_SDATA5, FN_SCIFA3_TXD, FN_I2C3_SDA_C, FN_DU1_DOTCLKOUT1,
+       FN_SSI_SCK6, FN_SCIFA1_SCK_B, FN_DU1_EXHSYNC_DU1_HSYNC,
+       FN_SSI_WS6, FN_SCIFA1_RXD_B, FN_I2C4_SCL_C, FN_DU1_EXVSYNC_DU1_VSYNC,
+       FN_SSI_SDATA6, FN_SCIFA1_TXD_B, FN_I2C4_SDA_C,
+       FN_DU1_EXODDF_DU1_ODDF_DISP_CDE,
+       FN_SSI_SCK78, FN_SCIFA2_SCK_B, FN_I2C5_SDA_C, FN_DU1_DISP,
+       FN_SSI_WS78, FN_SCIFA2_RXD_B, FN_I2C5_SCL_C, FN_DU1_CDE,
+       FN_SSI_SDATA7, FN_SCIFA2_TXD_B, FN_IRQ8, FN_AUDIO_CLKA_D, FN_CAN_CLK_D,
        FN_SSI_SCK0129, FN_MSIOF1_RXD_B, FN_SCIF5_RXD_D, FN_ADIDATA_B,
-       FN_AD_DI_B, FN_PCMWE_N, FN_SSI_WS0129, FN_MSIOF1_TXD_B, FN_SCIF5_TXD_D,
-       FN_ADICS_SAMP_B, FN_AD_DO_B, FN_SSI_SDATA0, FN_MSIOF1_SCK_B, FN_PWM0_B,
-       FN_ADICLK_B, FN_AD_CLK_B,
+       FN_SSI_WS0129, FN_MSIOF1_TXD_B, FN_SCIF5_TXD_D, FN_ADICS_SAMP_B,
+       FN_SSI_SDATA0, FN_MSIOF1_SCK_B, FN_PWM0_B, FN_ADICLK_B,
 
        /* IPSR12 */
        FN_SSI_SCK34, FN_MSIOF1_SYNC_B, FN_SCIFA1_SCK_C, FN_ADICHS0_B,
-       FN_AD_NCS_N_B, FN_DREQ1_N_B, FN_SSI_WS34, FN_MSIOF1_SS1_B,
-       FN_SCIFA1_RXD_C, FN_ADICHS1_B, FN_CAN1_RX_C, FN_DACK1_B, FN_SSI_SDATA3,
-       FN_MSIOF1_SS2_B, FN_SCIFA1_TXD_C, FN_ADICHS2_B, FN_CAN1_TX_C,
-       FN_DREQ2_N, FN_SSI_SCK4, FN_MLB_CLK, FN_IETX_B, FN_IRD_TX, FN_SSI_WS4,
-       FN_MLB_SIG, FN_IECLK_B, FN_IRD_RX, FN_SSI_SDATA4, FN_MLB_DAT,
-       FN_IERX_B, FN_IRD_SCK, FN_SSI_SDATA8, FN_SCIF1_SCK_B,
-       FN_PWM1_B, FN_IRQ9, FN_REMOCON, FN_DACK2, FN_ETH_MDIO_B, FN_SSI_SCK1,
-       FN_SCIF1_RXD_B, FN_IIC0_SCL_C, FN_VI1_CLK, FN_CAN0_RX_D,
-       FN_AVB_AVTP_CAPTURE, FN_ETH_CRS_DV_B, FN_SSI_WS1, FN_SCIF1_TXD_B,
-       FN_IIC0_SDA_C, FN_VI1_DATA0, FN_CAN0_TX_D, FN_AVB_AVTP_MATCH,
-       FN_ETH_RX_ER_B, FN_SSI_SDATA1, FN_HSCIF1_HRX_B, FN_SDATA, FN_VI1_DATA1,
-       FN_ATAWR0_N, FN_ETH_RXD0_B, FN_SSI_SCK2, FN_HSCIF1_HTX_B, FN_VI1_DATA2,
-       FN_MDATA, FN_ATAG0_N, FN_ETH_RXD1_B,
+       FN_DREQ1_N_B,
+       FN_SSI_WS34, FN_MSIOF1_SS1_B, FN_SCIFA1_RXD_C, FN_ADICHS1_B,
+       FN_CAN1_RX_C, FN_DACK1_B,
+       FN_SSI_SDATA3, FN_MSIOF1_SS2_B, FN_SCIFA1_TXD_C, FN_ADICHS2_B,
+       FN_CAN1_TX_C, FN_DREQ2_N,
+       FN_SSI_SCK4, FN_MLB_CLK, FN_IETX_B, FN_SSI_WS4, FN_MLB_SIG, FN_IECLK_B,
+       FN_SSI_SDATA4, FN_MLB_DAT, FN_IERX_B,
+       FN_SSI_SDATA8, FN_SCIF1_SCK_B, FN_PWM1_B, FN_IRQ9, FN_REMOCON,
+       FN_DACK2, FN_ETH_MDIO_B,
+       FN_SSI_SCK1, FN_SCIF1_RXD_B, FN_IIC0_SCL_C, FN_VI1_CLK, FN_CAN0_RX_D,
+       FN_ETH_CRS_DV_B,
+       FN_SSI_WS1, FN_SCIF1_TXD_B, FN_IIC0_SDA_C, FN_VI1_DATA0, FN_CAN0_TX_D,
+       FN_ETH_RX_ER_B,
+       FN_SSI_SDATA1, FN_HSCIF1_HRX_B, FN_VI1_DATA1, FN_ATAWR0_N,
+       FN_ETH_RXD0_B,
+       FN_SSI_SCK2, FN_HSCIF1_HTX_B, FN_VI1_DATA2, FN_ATAG0_N, FN_ETH_RXD1_B,
 
        /* IPSR13 */
-       FN_SSI_WS2, FN_HSCIF1_HCTS_N_B, FN_SCIFA0_RXD_D, FN_VI1_DATA3, FN_SCKZ,
-       FN_ATACS00_N, FN_ETH_LINK_B, FN_SSI_SDATA2, FN_HSCIF1_HRTS_N_B,
-       FN_SCIFA0_TXD_D, FN_VI1_DATA4, FN_STM_N, FN_ATACS10_N, FN_ETH_REFCLK_B,
-       FN_SSI_SCK9, FN_SCIF2_SCK_B, FN_PWM2_B, FN_VI1_DATA5, FN_MTS_N,
-       FN_EX_WAIT1, FN_ETH_TXD1_B, FN_SSI_WS9, FN_SCIF2_RXD_B, FN_I2C3_SCL_E,
-       FN_VI1_DATA6, FN_ATARD0_N, FN_ETH_TX_EN_B, FN_SSI_SDATA9,
-       FN_SCIF2_TXD_B, FN_I2C3_SDA_E, FN_VI1_DATA7, FN_ATADIR0_N,
-       FN_ETH_MAGIC_B, FN_AUDIO_CLKA, FN_I2C0_SCL_B, FN_SCIFA4_RXD_D,
-       FN_VI1_CLKENB, FN_TS_SDATA_C, FN_RIF0_SYNC_B, FN_ETH_TXD0_B,
+       FN_SSI_WS2, FN_HSCIF1_HCTS_N_B, FN_SCIFA0_RXD_D, FN_VI1_DATA3,
+       FN_ATACS00_N, FN_ETH_LINK_B,
+       FN_SSI_SDATA2, FN_HSCIF1_HRTS_N_B, FN_SCIFA0_TXD_D, FN_VI1_DATA4,
+       FN_ATACS10_N, FN_ETH_REFCLK_B,
+       FN_SSI_SCK9, FN_SCIF2_SCK_B, FN_PWM2_B, FN_VI1_DATA5, FN_EX_WAIT1,
+       FN_ETH_TXD1_B,
+       FN_SSI_WS9, FN_SCIF2_RXD_B, FN_I2C3_SCL_E, FN_VI1_DATA6, FN_ATARD0_N,
+       FN_ETH_TX_EN_B,
+       FN_SSI_SDATA9, FN_SCIF2_TXD_B, FN_I2C3_SDA_E, FN_VI1_DATA7,
+       FN_ATADIR0_N, FN_ETH_MAGIC_B,
+       FN_AUDIO_CLKA, FN_I2C0_SCL_B, FN_SCIFA4_RXD_D, FN_VI1_CLKENB,
+       FN_TS_SDATA_C, FN_ETH_TXD0_B,
        FN_AUDIO_CLKB, FN_I2C0_SDA_B, FN_SCIFA4_TXD_D, FN_VI1_FIELD,
-       FN_TS_SCK_C, FN_RIF0_CLK_B, FN_BPFCLK_E, FN_ETH_MDC_B, FN_AUDIO_CLKC,
-       FN_I2C4_SCL_B, FN_SCIFA5_RXD_D, FN_VI1_HSYNC_N, FN_TS_SDEN_C,
-       FN_RIF0_D0_B, FN_FMCLK_E, FN_RDS_CLK_D, FN_AUDIO_CLKOUT, FN_I2C4_SDA_B,
-       FN_SCIFA5_TXD_D, FN_VI1_VSYNC_N, FN_TS_SPSYNC_C, FN_RIF0_D1_B,
-       FN_FMIN_E, FN_RDS_DATA_D,
+       FN_TS_SCK_C, FN_BPFCLK_E, FN_ETH_MDC_B,
+       FN_AUDIO_CLKC, FN_I2C4_SCL_B, FN_SCIFA5_RXD_D, FN_VI1_HSYNC_N,
+       FN_TS_SDEN_C, FN_FMCLK_E,
+       FN_AUDIO_CLKOUT, FN_I2C4_SDA_B, FN_SCIFA5_TXD_D, FN_VI1_VSYNC_N,
+       FN_TS_SPSYNC_C, FN_FMIN_E,
 
        /* MOD_SEL */
        FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3,
-       FN_SEL_ADI_0, FN_SEL_ADI_1, FN_SEL_CAN_0, FN_SEL_CAN_1,
-       FN_SEL_CAN_2, FN_SEL_CAN_3, FN_SEL_DARC_0, FN_SEL_DARC_1,
-       FN_SEL_DARC_2, FN_SEL_DARC_3, FN_SEL_DARC_4, FN_SEL_DR0_0,
-       FN_SEL_DR0_1, FN_SEL_DR1_0, FN_SEL_DR1_1, FN_SEL_DR2_0, FN_SEL_DR2_1,
-       FN_SEL_DR3_0, FN_SEL_DR3_1, FN_SEL_ETH_0, FN_SEL_ETH_1, FN_SEL_FSN_0,
-       FN_SEL_FSN_1, FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2,
-       FN_SEL_I2C00_3, FN_SEL_I2C00_4, FN_SEL_I2C01_0, FN_SEL_I2C01_1,
-       FN_SEL_I2C01_2, FN_SEL_I2C01_3, FN_SEL_I2C01_4, FN_SEL_I2C02_0,
-       FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3, FN_SEL_I2C02_4,
+       FN_SEL_CAN_0, FN_SEL_CAN_1, FN_SEL_CAN_2, FN_SEL_CAN_3,
+       FN_SEL_DARC_0, FN_SEL_DARC_1, FN_SEL_DARC_2, FN_SEL_DARC_3,
+       FN_SEL_DARC_4,
+       FN_SEL_ETH_0, FN_SEL_ETH_1,
+       FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, FN_SEL_I2C00_3,
+       FN_SEL_I2C00_4,
+       FN_SEL_I2C01_0, FN_SEL_I2C01_1, FN_SEL_I2C01_2, FN_SEL_I2C01_3,
+       FN_SEL_I2C01_4,
+       FN_SEL_I2C02_0, FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3,
+       FN_SEL_I2C02_4,
        FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3,
-       FN_SEL_I2C03_4, FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2,
-       FN_SEL_I2C04_3, FN_SEL_I2C04_4, FN_SEL_I2C05_0, FN_SEL_I2C05_1,
-       FN_SEL_I2C05_2, FN_SEL_I2C05_3, FN_SEL_AVB_0, FN_SEL_AVB_1,
+       FN_SEL_I2C03_4,
+       FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2, FN_SEL_I2C04_3,
+       FN_SEL_I2C04_4,
+       FN_SEL_I2C05_0, FN_SEL_I2C05_1, FN_SEL_I2C05_2, FN_SEL_I2C05_3,
 
        /* MOD_SEL2 */
-       FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, FN_SEL_IIC0_0,
-       FN_SEL_IIC0_1, FN_SEL_IIC0_2, FN_SEL_IIC0_3, FN_SEL_LBS_0,
-       FN_SEL_LBS_1, FN_SEL_MSI1_0, FN_SEL_MSI1_1, FN_SEL_MSI2_0,
-       FN_SEL_MSI2_1, FN_SEL_RAD_0, FN_SEL_RAD_1, FN_SEL_RCN_0,
-       FN_SEL_RCN_1, FN_SEL_RSP_0, FN_SEL_RSP_1, FN_SEL_SCIFA0_0,
-       FN_SEL_SCIFA0_1, FN_SEL_SCIFA0_2, FN_SEL_SCIFA0_3, FN_SEL_SCIFA1_0,
-       FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
-       FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1,
-       FN_SEL_SCIFA4_2, FN_SEL_SCIFA4_3, FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1,
-       FN_SEL_SCIFA5_2, FN_SEL_SCIFA5_3, FN_SEL_SPDM_0, FN_SEL_SPDM_1,
-       FN_SEL_TMU_0, FN_SEL_TMU_1, FN_SEL_TSIF0_0, FN_SEL_TSIF0_1,
-       FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, FN_SEL_CAN0_0, FN_SEL_CAN0_1,
-       FN_SEL_CAN0_2, FN_SEL_CAN0_3, FN_SEL_CAN1_0, FN_SEL_CAN1_1,
-       FN_SEL_CAN1_2, FN_SEL_CAN1_3, FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1,
-       FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_RDS_0, FN_SEL_RDS_1,
-       FN_SEL_RDS_2, FN_SEL_RDS_3,
+       FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
+       FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, FN_SEL_IIC0_3,
+       FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_MSI1_0, FN_SEL_MSI1_1,
+       FN_SEL_MSI2_0, FN_SEL_MSI2_1, FN_SEL_RAD_0, FN_SEL_RAD_1,
+       FN_SEL_RCN_0, FN_SEL_RCN_1, FN_SEL_RSP_0, FN_SEL_RSP_1,
+       FN_SEL_SCIFA0_0, FN_SEL_SCIFA0_1, FN_SEL_SCIFA0_2, FN_SEL_SCIFA0_3,
+       FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2,
+       FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1,
+       FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2, FN_SEL_SCIFA4_3,
+       FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, FN_SEL_SCIFA5_3,
+       FN_SEL_TMU_0, FN_SEL_TMU_1,
+       FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
+       FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
+       FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
+       FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
 
        /* MOD_SEL3 */
        FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
@@ -372,117 +416,141 @@ enum {
        SCIF4_RXD_B_MARK, I2C0_SCL_D_MARK,
 
        /* IPSR1 */
-       D6_MARK, SCIF4_TXD_B_MARK, I2C0_SDA_D_MARK, D7_MARK, IRQ3_MARK,
-       TCLK1_MARK, PWM6_B_MARK, D8_MARK, HSCIF2_HRX_MARK, I2C1_SCL_B_MARK,
-       D9_MARK, HSCIF2_HTX_MARK, I2C1_SDA_B_MARK, D10_MARK,
-       HSCIF2_HSCK_MARK, SCIF1_SCK_C_MARK, IRQ6_MARK, PWM5_C_MARK,
+       D6_MARK, SCIF4_TXD_B_MARK, I2C0_SDA_D_MARK,
+       D7_MARK, IRQ3_MARK, TCLK1_MARK, PWM6_B_MARK,
+       D8_MARK, HSCIF2_HRX_MARK, I2C1_SCL_B_MARK,
+       D9_MARK, HSCIF2_HTX_MARK, I2C1_SDA_B_MARK,
+       D10_MARK, HSCIF2_HSCK_MARK, SCIF1_SCK_C_MARK, IRQ6_MARK, PWM5_C_MARK,
        D11_MARK, HSCIF2_HCTS_N_MARK, SCIF1_RXD_C_MARK, I2C1_SCL_D_MARK,
        D12_MARK, HSCIF2_HRTS_N_MARK, SCIF1_TXD_C_MARK, I2C1_SDA_D_MARK,
-       D13_MARK, SCIFA1_SCK_MARK, TANS1_MARK, PWM2_C_MARK, TCLK2_B_MARK,
-       D14_MARK, SCIFA1_RXD_MARK, I2C5_SCL_B_MARK, D15_MARK, SCIFA1_TXD_MARK,
-       I2C5_SDA_B_MARK, A0_MARK, SCIFB1_SCK_MARK, PWM3_B_MARK, A1_MARK,
-       SCIFB1_TXD_MARK, A3_MARK, SCIFB0_SCK_MARK, A4_MARK, SCIFB0_TXD_MARK,
-       A5_MARK, SCIFB0_RXD_MARK, PWM4_B_MARK, TPUTO3_C_MARK, A6_MARK,
-       SCIFB0_CTS_N_MARK, SCIFA4_RXD_B_MARK, TPUTO2_C_MARK,
+       D13_MARK, SCIFA1_SCK_MARK, PWM2_C_MARK, TCLK2_B_MARK,
+       D14_MARK, SCIFA1_RXD_MARK, I2C5_SCL_B_MARK,
+       D15_MARK, SCIFA1_TXD_MARK, I2C5_SDA_B_MARK,
+       A0_MARK, SCIFB1_SCK_MARK, PWM3_B_MARK,
+       A1_MARK, SCIFB1_TXD_MARK,
+       A3_MARK, SCIFB0_SCK_MARK,
+       A4_MARK, SCIFB0_TXD_MARK,
+       A5_MARK, SCIFB0_RXD_MARK, PWM4_B_MARK, TPUTO3_C_MARK,
+       A6_MARK, SCIFB0_CTS_N_MARK, SCIFA4_RXD_B_MARK, TPUTO2_C_MARK,
 
        /* IPSR2 */
-       A7_MARK, SCIFB0_RTS_N_MARK, SCIFA4_TXD_B_MARK, A8_MARK, MSIOF1_RXD_MARK,
-       SCIFA0_RXD_B_MARK, A9_MARK, MSIOF1_TXD_MARK, SCIFA0_TXD_B_MARK,
-       A10_MARK, MSIOF1_SCK_MARK, IIC0_SCL_B_MARK, A11_MARK, MSIOF1_SYNC_MARK,
-       IIC0_SDA_B_MARK, A12_MARK, MSIOF1_SS1_MARK, SCIFA5_RXD_B_MARK,
-       A13_MARK, MSIOF1_SS2_MARK, SCIFA5_TXD_B_MARK, A14_MARK, MSIOF2_RXD_MARK,
-       HSCIF0_HRX_B_MARK, DREQ1_N_MARK, A15_MARK, MSIOF2_TXD_MARK,
-       HSCIF0_HTX_B_MARK, DACK1_MARK, A16_MARK, MSIOF2_SCK_MARK,
-       HSCIF0_HSCK_B_MARK, SPEEDIN_MARK, VSP_MARK, CAN_CLK_C_MARK,
-       TPUTO2_B_MARK, A17_MARK, MSIOF2_SYNC_MARK, SCIF4_RXD_E_MARK,
-       CAN1_RX_B_MARK, AVB_AVTP_CAPTURE_B_MARK, A18_MARK, MSIOF2_SS1_MARK,
-       SCIF4_TXD_E_MARK, CAN1_TX_B_MARK, AVB_AVTP_MATCH_B_MARK, A19_MARK,
-       MSIOF2_SS2_MARK, PWM4_MARK, TPUTO2_MARK, MOUT0_MARK, A20_MARK,
-       SPCLK_MARK, MOUT1_MARK,
+       A7_MARK, SCIFB0_RTS_N_MARK, SCIFA4_TXD_B_MARK,
+       A8_MARK, MSIOF1_RXD_MARK, SCIFA0_RXD_B_MARK,
+       A9_MARK, MSIOF1_TXD_MARK, SCIFA0_TXD_B_MARK,
+       A10_MARK, MSIOF1_SCK_MARK, IIC0_SCL_B_MARK,
+       A11_MARK, MSIOF1_SYNC_MARK, IIC0_SDA_B_MARK,
+       A12_MARK, MSIOF1_SS1_MARK, SCIFA5_RXD_B_MARK,
+       A13_MARK, MSIOF1_SS2_MARK, SCIFA5_TXD_B_MARK,
+       A14_MARK, MSIOF2_RXD_MARK, HSCIF0_HRX_B_MARK, DREQ1_N_MARK,
+       A15_MARK, MSIOF2_TXD_MARK, HSCIF0_HTX_B_MARK, DACK1_MARK,
+       A16_MARK, MSIOF2_SCK_MARK, HSCIF0_HSCK_B_MARK, SPEEDIN_MARK,
+       CAN_CLK_C_MARK, TPUTO2_B_MARK,
+       A17_MARK, MSIOF2_SYNC_MARK, SCIF4_RXD_E_MARK, CAN1_RX_B_MARK,
+       A18_MARK, MSIOF2_SS1_MARK, SCIF4_TXD_E_MARK, CAN1_TX_B_MARK,
+       A19_MARK, MSIOF2_SS2_MARK, PWM4_MARK, TPUTO2_MARK,
+       A20_MARK, SPCLK_MARK,
 
        /* IPSR3 */
-       A21_MARK, MOSI_IO0_MARK, MOUT2_MARK, A22_MARK, MISO_IO1_MARK,
-       MOUT5_MARK, ATADIR1_N_MARK, A23_MARK, IO2_MARK, MOUT6_MARK,
-       ATAWR1_N_MARK, A24_MARK, IO3_MARK, EX_WAIT2_MARK, A25_MARK, SSL_MARK,
-       ATARD1_N_MARK, CS0_N_MARK, VI1_DATA8_MARK, CS1_N_A26_MARK,
-       VI1_DATA9_MARK, EX_CS0_N_MARK, VI1_DATA10_MARK, EX_CS1_N_MARK,
-       TPUTO3_B_MARK, SCIFB2_RXD_MARK, VI1_DATA11_MARK, EX_CS2_N_MARK,
-       PWM0_MARK, SCIF4_RXD_C_MARK, TS_SDATA_B_MARK, RIF0_SYNC_MARK,
-       TPUTO3_MARK, SCIFB2_TXD_MARK, SDATA_B_MARK, EX_CS3_N_MARK,
-       SCIFA2_SCK_MARK, SCIF4_TXD_C_MARK, TS_SCK_B_MARK, RIF0_CLK_MARK,
-       BPFCLK_MARK, SCIFB2_SCK_MARK, MDATA_B_MARK, EX_CS4_N_MARK,
-       SCIFA2_RXD_MARK, I2C2_SCL_E_MARK, TS_SDEN_B_MARK, RIF0_D0_MARK,
-       FMCLK_MARK, SCIFB2_CTS_N_MARK, SCKZ_B_MARK, EX_CS5_N_MARK,
-       SCIFA2_TXD_MARK, I2C2_SDA_E_MARK, TS_SPSYNC_B_MARK, RIF0_D1_MARK,
-       FMIN_MARK, SCIFB2_RTS_N_MARK, STM_N_B_MARK, BS_N_MARK, DRACK0_MARK,
-       PWM1_C_MARK, TPUTO0_C_MARK, ATACS01_N_MARK, MTS_N_B_MARK, RD_N_MARK,
-       ATACS11_N_MARK, RD_WR_N_MARK, ATAG1_N_MARK,
+       A21_MARK, MOSI_IO0_MARK,
+       A22_MARK, MISO_IO1_MARK, ATADIR1_N_MARK,
+       A23_MARK, IO2_MARK, ATAWR1_N_MARK,
+       A24_MARK, IO3_MARK, EX_WAIT2_MARK,
+       A25_MARK, SSL_MARK, ATARD1_N_MARK,
+       CS0_N_MARK, VI1_DATA8_MARK,
+       CS1_N_A26_MARK, VI1_DATA9_MARK,
+       EX_CS0_N_MARK, VI1_DATA10_MARK,
+       EX_CS1_N_MARK, TPUTO3_B_MARK, SCIFB2_RXD_MARK, VI1_DATA11_MARK,
+       EX_CS2_N_MARK, PWM0_MARK, SCIF4_RXD_C_MARK, TS_SDATA_B_MARK,
+       TPUTO3_MARK, SCIFB2_TXD_MARK,
+       EX_CS3_N_MARK, SCIFA2_SCK_MARK, SCIF4_TXD_C_MARK, TS_SCK_B_MARK,
+       BPFCLK_MARK, SCIFB2_SCK_MARK,
+       EX_CS4_N_MARK, SCIFA2_RXD_MARK, I2C2_SCL_E_MARK, TS_SDEN_B_MARK,
+       FMCLK_MARK, SCIFB2_CTS_N_MARK,
+       EX_CS5_N_MARK, SCIFA2_TXD_MARK, I2C2_SDA_E_MARK, TS_SPSYNC_B_MARK,
+       FMIN_MARK, SCIFB2_RTS_N_MARK,
+       BS_N_MARK, DRACK0_MARK, PWM1_C_MARK, TPUTO0_C_MARK, ATACS01_N_MARK,
+       RD_N_MARK, ATACS11_N_MARK,
+       RD_WR_N_MARK, ATAG1_N_MARK,
 
        /* IPSR4 */
-       EX_WAIT0_MARK, CAN_CLK_B_MARK, SCIF_CLK_MARK, PWMFSW0_MARK,
+       EX_WAIT0_MARK, CAN_CLK_B_MARK, SCIF_CLK_MARK,
        DU0_DR0_MARK, LCDOUT16_MARK, SCIF5_RXD_C_MARK, I2C2_SCL_D_MARK,
-       CC50_STATE0_MARK, DU0_DR1_MARK, LCDOUT17_MARK, SCIF5_TXD_C_MARK,
-       I2C2_SDA_D_MARK, CC50_STATE1_MARK, DU0_DR2_MARK, LCDOUT18_MARK,
-       CC50_STATE2_MARK, DU0_DR3_MARK, LCDOUT19_MARK, CC50_STATE3_MARK,
-       DU0_DR4_MARK, LCDOUT20_MARK, CC50_STATE4_MARK, DU0_DR5_MARK,
-       LCDOUT21_MARK, CC50_STATE5_MARK, DU0_DR6_MARK, LCDOUT22_MARK,
-       CC50_STATE6_MARK, DU0_DR7_MARK, LCDOUT23_MARK, CC50_STATE7_MARK,
+       DU0_DR1_MARK, LCDOUT17_MARK, SCIF5_TXD_C_MARK, I2C2_SDA_D_MARK,
+       DU0_DR2_MARK, LCDOUT18_MARK,
+       DU0_DR3_MARK, LCDOUT19_MARK,
+       DU0_DR4_MARK, LCDOUT20_MARK,
+       DU0_DR5_MARK, LCDOUT21_MARK,
+       DU0_DR6_MARK, LCDOUT22_MARK,
+       DU0_DR7_MARK, LCDOUT23_MARK,
        DU0_DG0_MARK, LCDOUT8_MARK, SCIFA0_RXD_C_MARK, I2C3_SCL_D_MARK,
-       CC50_STATE8_MARK, DU0_DG1_MARK, LCDOUT9_MARK, SCIFA0_TXD_C_MARK,
-       I2C3_SDA_D_MARK, CC50_STATE9_MARK, DU0_DG2_MARK, LCDOUT10_MARK,
-       CC50_STATE10_MARK, DU0_DG3_MARK, LCDOUT11_MARK, CC50_STATE11_MARK,
-       DU0_DG4_MARK, LCDOUT12_MARK, CC50_STATE12_MARK,
+       DU0_DG1_MARK, LCDOUT9_MARK, SCIFA0_TXD_C_MARK, I2C3_SDA_D_MARK,
+       DU0_DG2_MARK, LCDOUT10_MARK,
+       DU0_DG3_MARK, LCDOUT11_MARK,
+       DU0_DG4_MARK, LCDOUT12_MARK,
 
        /* IPSR5 */
-       DU0_DG5_MARK, LCDOUT13_MARK, CC50_STATE13_MARK, DU0_DG6_MARK,
-       LCDOUT14_MARK, CC50_STATE14_MARK, DU0_DG7_MARK, LCDOUT15_MARK,
-       CC50_STATE15_MARK, DU0_DB0_MARK, LCDOUT0_MARK, SCIFA4_RXD_C_MARK,
-       I2C4_SCL_D_MARK, CAN0_RX_C_MARK, CC50_STATE16_MARK, DU0_DB1_MARK,
-       LCDOUT1_MARK, SCIFA4_TXD_C_MARK, I2C4_SDA_D_MARK, CAN0_TX_C_MARK,
-       CC50_STATE17_MARK, DU0_DB2_MARK, LCDOUT2_MARK, CC50_STATE18_MARK,
-       DU0_DB3_MARK, LCDOUT3_MARK, CC50_STATE19_MARK, DU0_DB4_MARK,
-       LCDOUT4_MARK, CC50_STATE20_MARK, DU0_DB5_MARK, LCDOUT5_MARK,
-       CC50_STATE21_MARK, DU0_DB6_MARK, LCDOUT6_MARK, CC50_STATE22_MARK,
-       DU0_DB7_MARK, LCDOUT7_MARK, CC50_STATE23_MARK, DU0_DOTCLKIN_MARK,
-       QSTVA_QVS_MARK, CC50_STATE24_MARK, DU0_DOTCLKOUT0_MARK,
-       QCLK_MARK, CC50_STATE25_MARK, DU0_DOTCLKOUT1_MARK, QSTVB_QVE_MARK,
-       CC50_STATE26_MARK, DU0_EXHSYNC_DU0_HSYNC_MARK, QSTH_QHS_MARK,
-       CC50_STATE27_MARK,
+       DU0_DG5_MARK, LCDOUT13_MARK,
+       DU0_DG6_MARK, LCDOUT14_MARK,
+       DU0_DG7_MARK, LCDOUT15_MARK,
+       DU0_DB0_MARK, LCDOUT0_MARK, SCIFA4_RXD_C_MARK, I2C4_SCL_D_MARK,
+       CAN0_RX_C_MARK,
+       DU0_DB1_MARK, LCDOUT1_MARK, SCIFA4_TXD_C_MARK, I2C4_SDA_D_MARK,
+       CAN0_TX_C_MARK,
+       DU0_DB2_MARK, LCDOUT2_MARK,
+       DU0_DB3_MARK, LCDOUT3_MARK,
+       DU0_DB4_MARK, LCDOUT4_MARK,
+       DU0_DB5_MARK, LCDOUT5_MARK,
+       DU0_DB6_MARK, LCDOUT6_MARK,
+       DU0_DB7_MARK, LCDOUT7_MARK,
+       DU0_DOTCLKIN_MARK, QSTVA_QVS_MARK,
+       DU0_DOTCLKOUT0_MARK, QCLK_MARK,
+       DU0_DOTCLKOUT1_MARK, QSTVB_QVE_MARK,
+       DU0_EXHSYNC_DU0_HSYNC_MARK, QSTH_QHS_MARK,
 
        /* IPSR6 */
-       DU0_EXVSYNC_DU0_VSYNC_MARK, QSTB_QHE_MARK, CC50_STATE28_MARK,
-       DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK, CC50_STATE29_MARK,
-       DU0_DISP_MARK, QPOLA_MARK, CC50_STATE30_MARK, DU0_CDE_MARK, QPOLB_MARK,
-       CC50_STATE31_MARK, VI0_CLK_MARK, AVB_RX_CLK_MARK, VI0_DATA0_VI0_B0_MARK,
-       AVB_RX_DV_MARK, VI0_DATA1_VI0_B1_MARK, AVB_RXD0_MARK,
-       VI0_DATA2_VI0_B2_MARK, AVB_RXD1_MARK, VI0_DATA3_VI0_B3_MARK,
-       AVB_RXD2_MARK, VI0_DATA4_VI0_B4_MARK, AVB_RXD3_MARK,
-       VI0_DATA5_VI0_B5_MARK, AVB_RXD4_MARK, VI0_DATA6_VI0_B6_MARK,
-       AVB_RXD5_MARK, VI0_DATA7_VI0_B7_MARK, AVB_RXD6_MARK, VI0_CLKENB_MARK,
-       I2C3_SCL_MARK, SCIFA5_RXD_C_MARK, IETX_C_MARK, AVB_RXD7_MARK,
+       DU0_EXVSYNC_DU0_VSYNC_MARK, QSTB_QHE_MARK,
+       DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK,
+       DU0_DISP_MARK, QPOLA_MARK, DU0_CDE_MARK, QPOLB_MARK,
+       VI0_CLK_MARK, AVB_RX_CLK_MARK, VI0_DATA0_VI0_B0_MARK, AVB_RX_DV_MARK,
+       VI0_DATA1_VI0_B1_MARK, AVB_RXD0_MARK,
+       VI0_DATA2_VI0_B2_MARK, AVB_RXD1_MARK,
+       VI0_DATA3_VI0_B3_MARK, AVB_RXD2_MARK,
+       VI0_DATA4_VI0_B4_MARK, AVB_RXD3_MARK,
+       VI0_DATA5_VI0_B5_MARK, AVB_RXD4_MARK,
+       VI0_DATA6_VI0_B6_MARK, AVB_RXD5_MARK,
+       VI0_DATA7_VI0_B7_MARK, AVB_RXD6_MARK,
+       VI0_CLKENB_MARK, I2C3_SCL_MARK, SCIFA5_RXD_C_MARK, IETX_C_MARK,
+       AVB_RXD7_MARK,
        VI0_FIELD_MARK, I2C3_SDA_MARK, SCIFA5_TXD_C_MARK, IECLK_C_MARK,
-       AVB_RX_ER_MARK, VI0_HSYNC_N_MARK, SCIF0_RXD_B_MARK, I2C0_SCL_C_MARK,
-       IERX_C_MARK, AVB_COL_MARK, VI0_VSYNC_N_MARK, SCIF0_TXD_B_MARK,
-       I2C0_SDA_C_MARK, AUDIO_CLKOUT_B_MARK, AVB_TX_EN_MARK, ETH_MDIO_MARK,
-       VI0_G0_MARK, MSIOF2_RXD_B_MARK, I2C5_SCL_D_MARK, AVB_TX_CLK_MARK,
-       ADIDATA_MARK, AD_DI_MARK,
+       AVB_RX_ER_MARK,
+       VI0_HSYNC_N_MARK, SCIF0_RXD_B_MARK, I2C0_SCL_C_MARK, IERX_C_MARK,
+       AVB_COL_MARK,
+       VI0_VSYNC_N_MARK, SCIF0_TXD_B_MARK, I2C0_SDA_C_MARK,
+       AUDIO_CLKOUT_B_MARK, AVB_TX_EN_MARK,
+       ETH_MDIO_MARK, VI0_G0_MARK, MSIOF2_RXD_B_MARK, I2C5_SCL_D_MARK,
+       AVB_TX_CLK_MARK, ADIDATA_MARK,
 
        /* IPSR7 */
        ETH_CRS_DV_MARK, VI0_G1_MARK, MSIOF2_TXD_B_MARK, I2C5_SDA_D_MARK,
-       AVB_TXD0_MARK, ADICS_SAMP_MARK, AD_DO_MARK, ETH_RX_ER_MARK, VI0_G2_MARK,
-       MSIOF2_SCK_B_MARK, CAN0_RX_B_MARK, AVB_TXD1_MARK, ADICLK_MARK,
-       AD_CLK_MARK, ETH_RXD0_MARK, VI0_G3_MARK, MSIOF2_SYNC_B_MARK,
-       CAN0_TX_B_MARK, AVB_TXD2_MARK, ADICHS0_MARK, AD_NCS_N_MARK,
+       AVB_TXD0_MARK, ADICS_SAMP_MARK,
+       ETH_RX_ER_MARK, VI0_G2_MARK, MSIOF2_SCK_B_MARK, CAN0_RX_B_MARK,
+       AVB_TXD1_MARK, ADICLK_MARK,
+       ETH_RXD0_MARK, VI0_G3_MARK, MSIOF2_SYNC_B_MARK, CAN0_TX_B_MARK,
+       AVB_TXD2_MARK, ADICHS0_MARK,
        ETH_RXD1_MARK, VI0_G4_MARK, MSIOF2_SS1_B_MARK, SCIF4_RXD_D_MARK,
-       AVB_TXD3_MARK, ADICHS1_MARK, ETH_LINK_MARK, VI0_G5_MARK,
-       MSIOF2_SS2_B_MARK, SCIF4_TXD_D_MARK, AVB_TXD4_MARK, ADICHS2_MARK,
+       AVB_TXD3_MARK, ADICHS1_MARK,
+       ETH_LINK_MARK, VI0_G5_MARK, MSIOF2_SS2_B_MARK, SCIF4_TXD_D_MARK,
+       AVB_TXD4_MARK, ADICHS2_MARK,
        ETH_REFCLK_MARK, VI0_G6_MARK, SCIF2_SCK_C_MARK, AVB_TXD5_MARK,
-       SSI_SCK5_B_MARK, ETH_TXD1_MARK, VI0_G7_MARK, SCIF2_RXD_C_MARK,
-       IIC0_SCL_D_MARK, AVB_TXD6_MARK, SSI_WS5_B_MARK, ETH_TX_EN_MARK,
-       VI0_R0_MARK, SCIF2_TXD_C_MARK, IIC0_SDA_D_MARK, AVB_TXD7_MARK,
-       SSI_SDATA5_B_MARK, ETH_MAGIC_MARK, VI0_R1_MARK, SCIF3_SCK_B_MARK,
-       AVB_TX_ER_MARK, SSI_SCK6_B_MARK, ETH_TXD0_MARK, VI0_R2_MARK,
-       SCIF3_RXD_B_MARK, I2C4_SCL_E_MARK, AVB_GTX_CLK_MARK, SSI_WS6_B_MARK,
+       SSI_SCK5_B_MARK,
+       ETH_TXD1_MARK, VI0_G7_MARK, SCIF2_RXD_C_MARK, IIC0_SCL_D_MARK,
+       AVB_TXD6_MARK, SSI_WS5_B_MARK,
+       ETH_TX_EN_MARK, VI0_R0_MARK, SCIF2_TXD_C_MARK, IIC0_SDA_D_MARK,
+       AVB_TXD7_MARK, SSI_SDATA5_B_MARK,
+       ETH_MAGIC_MARK, VI0_R1_MARK, SCIF3_SCK_B_MARK, AVB_TX_ER_MARK,
+       SSI_SCK6_B_MARK,
+       ETH_TXD0_MARK, VI0_R2_MARK, SCIF3_RXD_B_MARK, I2C4_SCL_E_MARK,
+       AVB_GTX_CLK_MARK, SSI_WS6_B_MARK,
        DREQ0_N_MARK, SCIFB1_RXD_MARK,
 
        /* IPSR8 */
@@ -498,103 +566,107 @@ enum {
        I2C0_SCL_MARK, SCIF0_RXD_C_MARK, PWM5_MARK, TCLK1_B_MARK,
        AVB_GTXREFCLK_MARK, CAN1_RX_D_MARK, TPUTO0_B_MARK, I2C0_SDA_MARK,
        SCIF0_TXD_C_MARK, TPUTO0_MARK, CAN_CLK_MARK, DVC_MUTE_MARK,
-       CAN1_TX_D_MARK, I2C1_SCL_MARK, SCIF4_RXD_MARK, PWM5_B_MARK,
-       DU1_DR0_MARK, RIF1_SYNC_B_MARK, TS_SDATA_D_MARK, TPUTO1_B_MARK,
-       I2C1_SDA_MARK, SCIF4_TXD_MARK, IRQ5_MARK, DU1_DR1_MARK, RIF1_CLK_B_MARK,
-       TS_SCK_D_MARK, BPFCLK_C_MARK, MSIOF0_RXD_MARK, SCIF5_RXD_MARK,
-       I2C2_SCL_C_MARK, DU1_DR2_MARK, RIF1_D0_B_MARK, TS_SDEN_D_MARK,
-       FMCLK_C_MARK, RDS_CLK_MARK,
+       CAN1_TX_D_MARK,
+       I2C1_SCL_MARK, SCIF4_RXD_MARK, PWM5_B_MARK, DU1_DR0_MARK,
+       TS_SDATA_D_MARK, TPUTO1_B_MARK,
+       I2C1_SDA_MARK, SCIF4_TXD_MARK, IRQ5_MARK, DU1_DR1_MARK, TS_SCK_D_MARK,
+       BPFCLK_C_MARK,
+       MSIOF0_RXD_MARK, SCIF5_RXD_MARK, I2C2_SCL_C_MARK, DU1_DR2_MARK,
+       TS_SDEN_D_MARK, FMCLK_C_MARK,
 
        /* IPSR9 */
        MSIOF0_TXD_MARK, SCIF5_TXD_MARK, I2C2_SDA_C_MARK, DU1_DR3_MARK,
-       RIF1_D1_B_MARK, TS_SPSYNC_D_MARK, FMIN_C_MARK, RDS_DATA_MARK,
-       MSIOF0_SCK_MARK, IRQ0_MARK, TS_SDATA_MARK, DU1_DR4_MARK, RIF1_SYNC_MARK,
-       TPUTO1_C_MARK, MSIOF0_SYNC_MARK, PWM1_MARK, TS_SCK_MARK, DU1_DR5_MARK,
-       RIF1_CLK_MARK, BPFCLK_B_MARK, MSIOF0_SS1_MARK, SCIFA0_RXD_MARK,
-       TS_SDEN_MARK, DU1_DR6_MARK, RIF1_D0_MARK, FMCLK_B_MARK, RDS_CLK_B_MARK,
+       TS_SPSYNC_D_MARK, FMIN_C_MARK,
+       MSIOF0_SCK_MARK, IRQ0_MARK, TS_SDATA_MARK, DU1_DR4_MARK, TPUTO1_C_MARK,
+       MSIOF0_SYNC_MARK, PWM1_MARK, TS_SCK_MARK, DU1_DR5_MARK, BPFCLK_B_MARK,
+       MSIOF0_SS1_MARK, SCIFA0_RXD_MARK, TS_SDEN_MARK, DU1_DR6_MARK,
+       FMCLK_B_MARK,
        MSIOF0_SS2_MARK, SCIFA0_TXD_MARK, TS_SPSYNC_MARK, DU1_DR7_MARK,
-       RIF1_D1_MARK, FMIN_B_MARK, RDS_DATA_B_MARK, HSCIF1_HRX_MARK,
-       I2C4_SCL_MARK, PWM6_MARK, DU1_DG0_MARK, HSCIF1_HTX_MARK,
-       I2C4_SDA_MARK, TPUTO1_MARK, DU1_DG1_MARK, HSCIF1_HSCK_MARK,
-       PWM2_MARK, IETX_MARK, DU1_DG2_MARK, REMOCON_B_MARK, SPEEDIN_B_MARK,
-       VSP_B_MARK, HSCIF1_HCTS_N_MARK, SCIFA4_RXD_MARK, IECLK_MARK,
-       DU1_DG3_MARK, SSI_SCK1_B_MARK, CAN_DEBUG_HW_TRIGGER_MARK,
-       CC50_STATE32_MARK, HSCIF1_HRTS_N_MARK, SCIFA4_TXD_MARK, IERX_MARK,
-       DU1_DG4_MARK, SSI_WS1_B_MARK, CAN_STEP0_MARK, CC50_STATE33_MARK,
+       FMIN_B_MARK,
+       HSCIF1_HRX_MARK, I2C4_SCL_MARK, PWM6_MARK, DU1_DG0_MARK,
+       HSCIF1_HTX_MARK, I2C4_SDA_MARK, TPUTO1_MARK, DU1_DG1_MARK,
+       HSCIF1_HSCK_MARK, PWM2_MARK, IETX_MARK, DU1_DG2_MARK, REMOCON_B_MARK,
+       SPEEDIN_B_MARK,
+       HSCIF1_HCTS_N_MARK, SCIFA4_RXD_MARK, IECLK_MARK, DU1_DG3_MARK,
+       SSI_SCK1_B_MARK,
+       HSCIF1_HRTS_N_MARK, SCIFA4_TXD_MARK, IERX_MARK, DU1_DG4_MARK,
+       SSI_WS1_B_MARK,
        SCIF1_SCK_MARK, PWM3_MARK, TCLK2_MARK, DU1_DG5_MARK, SSI_SDATA1_B_MARK,
-       CAN_TXCLK_MARK, CC50_STATE34_MARK,
+       CAN_TXCLK_MARK,
 
        /* IPSR10 */
        SCIF1_RXD_MARK, I2C5_SCL_MARK, DU1_DG6_MARK, SSI_SCK2_B_MARK,
-       CAN_DEBUGOUT0_MARK, CC50_STATE35_MARK, SCIF1_TXD_MARK, I2C5_SDA_MARK,
-       DU1_DG7_MARK, SSI_WS2_B_MARK, CAN_DEBUGOUT1_MARK, CC50_STATE36_MARK,
+       SCIF1_TXD_MARK, I2C5_SDA_MARK, DU1_DG7_MARK, SSI_WS2_B_MARK,
        SCIF2_RXD_MARK, IIC0_SCL_MARK, DU1_DB0_MARK, SSI_SDATA2_B_MARK,
-       USB0_EXTLP_MARK, CAN_DEBUGOUT2_MARK, CC50_STATE37_MARK, SCIF2_TXD_MARK,
-       IIC0_SDA_MARK, DU1_DB1_MARK, SSI_SCK9_B_MARK, USB0_OVC1_MARK,
-       CAN_DEBUGOUT3_MARK, CC50_STATE38_MARK, SCIF2_SCK_MARK, IRQ1_MARK,
-       DU1_DB2_MARK, SSI_WS9_B_MARK, USB0_IDIN_MARK, CAN_DEBUGOUT4_MARK,
-       CC50_STATE39_MARK, SCIF3_SCK_MARK, IRQ2_MARK, BPFCLK_D_MARK,
-       DU1_DB3_MARK, SSI_SDATA9_B_MARK, TANS2_MARK, CAN_DEBUGOUT5_MARK,
-       CC50_OSCOUT_MARK, SCIF3_RXD_MARK, I2C1_SCL_E_MARK, FMCLK_D_MARK,
-       DU1_DB4_MARK, AUDIO_CLKA_C_MARK, SSI_SCK4_B_MARK, CAN_DEBUGOUT6_MARK,
-       RDS_CLK_C_MARK, SCIF3_TXD_MARK, I2C1_SDA_E_MARK, FMIN_D_MARK,
-       DU1_DB5_MARK, AUDIO_CLKB_C_MARK, SSI_WS4_B_MARK, CAN_DEBUGOUT7_MARK,
-       RDS_DATA_C_MARK, I2C2_SCL_MARK, SCIFA5_RXD_MARK, DU1_DB6_MARK,
-       AUDIO_CLKC_C_MARK, SSI_SDATA4_B_MARK, CAN_DEBUGOUT8_MARK, I2C2_SDA_MARK,
-       SCIFA5_TXD_MARK, DU1_DB7_MARK, AUDIO_CLKOUT_C_MARK, CAN_DEBUGOUT9_MARK,
-       SSI_SCK5_MARK, SCIFA3_SCK_MARK, DU1_DOTCLKIN_MARK, CAN_DEBUGOUT10_MARK,
+       SCIF2_TXD_MARK, IIC0_SDA_MARK, DU1_DB1_MARK, SSI_SCK9_B_MARK,
+       SCIF2_SCK_MARK, IRQ1_MARK, DU1_DB2_MARK, SSI_WS9_B_MARK,
+       SCIF3_SCK_MARK, IRQ2_MARK, BPFCLK_D_MARK, DU1_DB3_MARK,
+       SSI_SDATA9_B_MARK,
+       SCIF3_RXD_MARK, I2C1_SCL_E_MARK, FMCLK_D_MARK, DU1_DB4_MARK,
+       AUDIO_CLKA_C_MARK, SSI_SCK4_B_MARK,
+       SCIF3_TXD_MARK, I2C1_SDA_E_MARK, FMIN_D_MARK, DU1_DB5_MARK,
+       AUDIO_CLKB_C_MARK, SSI_WS4_B_MARK,
+       I2C2_SCL_MARK, SCIFA5_RXD_MARK, DU1_DB6_MARK, AUDIO_CLKC_C_MARK,
+       SSI_SDATA4_B_MARK,
+       I2C2_SDA_MARK, SCIFA5_TXD_MARK, DU1_DB7_MARK, AUDIO_CLKOUT_C_MARK,
+       SSI_SCK5_MARK, SCIFA3_SCK_MARK, DU1_DOTCLKIN_MARK,
 
        /* IPSR11 */
        SSI_WS5_MARK, SCIFA3_RXD_MARK, I2C3_SCL_C_MARK, DU1_DOTCLKOUT0_MARK,
-       CAN_DEBUGOUT11_MARK, SSI_SDATA5_MARK, SCIFA3_TXD_MARK, I2C3_SDA_C_MARK,
-       DU1_DOTCLKOUT1_MARK, CAN_DEBUGOUT12_MARK, SSI_SCK6_MARK,
-       SCIFA1_SCK_B_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK, CAN_DEBUGOUT13_MARK,
+       SSI_SDATA5_MARK, SCIFA3_TXD_MARK, I2C3_SDA_C_MARK, DU1_DOTCLKOUT1_MARK,
+       SSI_SCK6_MARK, SCIFA1_SCK_B_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK,
        SSI_WS6_MARK, SCIFA1_RXD_B_MARK, I2C4_SCL_C_MARK,
-       DU1_EXVSYNC_DU1_VSYNC_MARK, CAN_DEBUGOUT14_MARK, SSI_SDATA6_MARK,
-       SCIFA1_TXD_B_MARK, I2C4_SDA_C_MARK, DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
-       CAN_DEBUGOUT15_MARK, SSI_SCK78_MARK, SCIFA2_SCK_B_MARK, I2C5_SDA_C_MARK,
-       DU1_DISP_MARK, SSI_WS78_MARK, SCIFA2_RXD_B_MARK, I2C5_SCL_C_MARK,
-       DU1_CDE_MARK, SSI_SDATA7_MARK, SCIFA2_TXD_B_MARK, IRQ8_MARK,
-       AUDIO_CLKA_D_MARK, CAN_CLK_D_MARK, PCMOE_N_MARK, SSI_SCK0129_MARK,
-       MSIOF1_RXD_B_MARK, SCIF5_RXD_D_MARK, ADIDATA_B_MARK, AD_DI_B_MARK,
-       PCMWE_N_MARK, SSI_WS0129_MARK, MSIOF1_TXD_B_MARK, SCIF5_TXD_D_MARK,
-       ADICS_SAMP_B_MARK, AD_DO_B_MARK, SSI_SDATA0_MARK, MSIOF1_SCK_B_MARK,
-       PWM0_B_MARK, ADICLK_B_MARK, AD_CLK_B_MARK,
+       DU1_EXVSYNC_DU1_VSYNC_MARK,
+       SSI_SDATA6_MARK, SCIFA1_TXD_B_MARK, I2C4_SDA_C_MARK,
+       DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
+       SSI_SCK78_MARK, SCIFA2_SCK_B_MARK, I2C5_SDA_C_MARK, DU1_DISP_MARK,
+       SSI_WS78_MARK, SCIFA2_RXD_B_MARK, I2C5_SCL_C_MARK, DU1_CDE_MARK,
+       SSI_SDATA7_MARK, SCIFA2_TXD_B_MARK, IRQ8_MARK, AUDIO_CLKA_D_MARK,
+       CAN_CLK_D_MARK,
+       SSI_SCK0129_MARK, MSIOF1_RXD_B_MARK, SCIF5_RXD_D_MARK, ADIDATA_B_MARK,
+       SSI_WS0129_MARK, MSIOF1_TXD_B_MARK, SCIF5_TXD_D_MARK, ADICS_SAMP_B_MARK,
+       SSI_SDATA0_MARK, MSIOF1_SCK_B_MARK, PWM0_B_MARK, ADICLK_B_MARK,
 
        /* IPSR12 */
        SSI_SCK34_MARK, MSIOF1_SYNC_B_MARK, SCIFA1_SCK_C_MARK, ADICHS0_B_MARK,
-       AD_NCS_N_B_MARK, DREQ1_N_B_MARK, SSI_WS34_MARK, MSIOF1_SS1_B_MARK,
-       SCIFA1_RXD_C_MARK, ADICHS1_B_MARK, CAN1_RX_C_MARK, DACK1_B_MARK,
+       DREQ1_N_B_MARK,
+       SSI_WS34_MARK, MSIOF1_SS1_B_MARK, SCIFA1_RXD_C_MARK, ADICHS1_B_MARK,
+       CAN1_RX_C_MARK, DACK1_B_MARK,
        SSI_SDATA3_MARK, MSIOF1_SS2_B_MARK, SCIFA1_TXD_C_MARK, ADICHS2_B_MARK,
-       CAN1_TX_C_MARK, DREQ2_N_MARK, SSI_SCK4_MARK, MLB_CLK_MARK, IETX_B_MARK,
-       IRD_TX_MARK, SSI_WS4_MARK, MLB_SIG_MARK, IECLK_B_MARK, IRD_RX_MARK,
-       SSI_SDATA4_MARK, MLB_DAT_MARK, IERX_B_MARK, IRD_SCK_MARK,
+       CAN1_TX_C_MARK, DREQ2_N_MARK,
+       SSI_SCK4_MARK, MLB_CLK_MARK, IETX_B_MARK,
+       SSI_WS4_MARK, MLB_SIG_MARK, IECLK_B_MARK,
+       SSI_SDATA4_MARK, MLB_DAT_MARK, IERX_B_MARK,
        SSI_SDATA8_MARK, SCIF1_SCK_B_MARK, PWM1_B_MARK, IRQ9_MARK, REMOCON_MARK,
-       DACK2_MARK, ETH_MDIO_B_MARK, SSI_SCK1_MARK, SCIF1_RXD_B_MARK,
-       IIC0_SCL_C_MARK, VI1_CLK_MARK, CAN0_RX_D_MARK, AVB_AVTP_CAPTURE_MARK,
-       ETH_CRS_DV_B_MARK, SSI_WS1_MARK, SCIF1_TXD_B_MARK, IIC0_SDA_C_MARK,
-       VI1_DATA0_MARK, CAN0_TX_D_MARK, AVB_AVTP_MATCH_MARK, ETH_RX_ER_B_MARK,
-       SSI_SDATA1_MARK, HSCIF1_HRX_B_MARK, VI1_DATA1_MARK, SDATA_MARK,
-       ATAWR0_N_MARK, ETH_RXD0_B_MARK, SSI_SCK2_MARK, HSCIF1_HTX_B_MARK,
-       VI1_DATA2_MARK, MDATA_MARK, ATAG0_N_MARK, ETH_RXD1_B_MARK,
+       DACK2_MARK, ETH_MDIO_B_MARK,
+       SSI_SCK1_MARK, SCIF1_RXD_B_MARK, IIC0_SCL_C_MARK, VI1_CLK_MARK,
+       CAN0_RX_D_MARK, ETH_CRS_DV_B_MARK,
+       SSI_WS1_MARK, SCIF1_TXD_B_MARK, IIC0_SDA_C_MARK, VI1_DATA0_MARK,
+       CAN0_TX_D_MARK, ETH_RX_ER_B_MARK,
+       SSI_SDATA1_MARK, HSCIF1_HRX_B_MARK, VI1_DATA1_MARK, ATAWR0_N_MARK,
+       ETH_RXD0_B_MARK,
+       SSI_SCK2_MARK, HSCIF1_HTX_B_MARK, VI1_DATA2_MARK, ATAG0_N_MARK,
+       ETH_RXD1_B_MARK,
 
        /* IPSR13 */
        SSI_WS2_MARK, HSCIF1_HCTS_N_B_MARK, SCIFA0_RXD_D_MARK, VI1_DATA3_MARK,
-       SCKZ_MARK, ATACS00_N_MARK, ETH_LINK_B_MARK, SSI_SDATA2_MARK,
-       HSCIF1_HRTS_N_B_MARK, SCIFA0_TXD_D_MARK, VI1_DATA4_MARK, STM_N_MARK,
-       ATACS10_N_MARK, ETH_REFCLK_B_MARK, SSI_SCK9_MARK, SCIF2_SCK_B_MARK,
-       PWM2_B_MARK, VI1_DATA5_MARK, MTS_N_MARK, EX_WAIT1_MARK,
-       ETH_TXD1_B_MARK, SSI_WS9_MARK, SCIF2_RXD_B_MARK, I2C3_SCL_E_MARK,
-       VI1_DATA6_MARK, ATARD0_N_MARK, ETH_TX_EN_B_MARK, SSI_SDATA9_MARK,
-       SCIF2_TXD_B_MARK, I2C3_SDA_E_MARK, VI1_DATA7_MARK, ATADIR0_N_MARK,
-       ETH_MAGIC_B_MARK, AUDIO_CLKA_MARK, I2C0_SCL_B_MARK, SCIFA4_RXD_D_MARK,
-       VI1_CLKENB_MARK, TS_SDATA_C_MARK, RIF0_SYNC_B_MARK, ETH_TXD0_B_MARK,
+       ATACS00_N_MARK, ETH_LINK_B_MARK,
+       SSI_SDATA2_MARK, HSCIF1_HRTS_N_B_MARK, SCIFA0_TXD_D_MARK,
+       VI1_DATA4_MARK, ATACS10_N_MARK, ETH_REFCLK_B_MARK,
+       SSI_SCK9_MARK, SCIF2_SCK_B_MARK, PWM2_B_MARK, VI1_DATA5_MARK,
+       EX_WAIT1_MARK, ETH_TXD1_B_MARK,
+       SSI_WS9_MARK, SCIF2_RXD_B_MARK, I2C3_SCL_E_MARK, VI1_DATA6_MARK,
+       ATARD0_N_MARK, ETH_TX_EN_B_MARK,
+       SSI_SDATA9_MARK, SCIF2_TXD_B_MARK, I2C3_SDA_E_MARK, VI1_DATA7_MARK,
+       ATADIR0_N_MARK, ETH_MAGIC_B_MARK,
+       AUDIO_CLKA_MARK, I2C0_SCL_B_MARK, SCIFA4_RXD_D_MARK, VI1_CLKENB_MARK,
+       TS_SDATA_C_MARK, ETH_TXD0_B_MARK,
        AUDIO_CLKB_MARK, I2C0_SDA_B_MARK, SCIFA4_TXD_D_MARK, VI1_FIELD_MARK,
-       TS_SCK_C_MARK, RIF0_CLK_B_MARK, BPFCLK_E_MARK, ETH_MDC_B_MARK,
+       TS_SCK_C_MARK, BPFCLK_E_MARK, ETH_MDC_B_MARK,
        AUDIO_CLKC_MARK, I2C4_SCL_B_MARK, SCIFA5_RXD_D_MARK, VI1_HSYNC_N_MARK,
-       TS_SDEN_C_MARK, RIF0_D0_B_MARK, FMCLK_E_MARK, RDS_CLK_D_MARK,
+       TS_SDEN_C_MARK, FMCLK_E_MARK,
        AUDIO_CLKOUT_MARK, I2C4_SDA_B_MARK, SCIFA5_TXD_D_MARK, VI1_VSYNC_N_MARK,
-       TS_SPSYNC_C_MARK, RIF0_D1_B_MARK, FMIN_E_MARK, RDS_DATA_D_MARK,
+       TS_SPSYNC_C_MARK, FMIN_E_MARK,
        PINMUX_MARK_END,
 };
 
@@ -700,7 +772,6 @@ static const u16 pinmux_data[] = {
        PINMUX_IPSR_MSEL(IP1_14_13, I2C1_SDA_D, SEL_I2C01_3),
        PINMUX_IPSR_GPSR(IP1_17_15, D13),
        PINMUX_IPSR_MSEL(IP1_17_15, SCIFA1_SCK, SEL_SCIFA1_0),
-       PINMUX_IPSR_GPSR(IP1_17_15, TANS1),
        PINMUX_IPSR_GPSR(IP1_17_15, PWM2_C),
        PINMUX_IPSR_MSEL(IP1_17_15, TCLK2_B, SEL_TMU_1),
        PINMUX_IPSR_GPSR(IP1_19_18, D14),
@@ -761,39 +832,31 @@ static const u16 pinmux_data[] = {
        PINMUX_IPSR_MSEL(IP2_20_18, MSIOF2_SCK, SEL_MSI2_0),
        PINMUX_IPSR_MSEL(IP2_20_18, HSCIF0_HSCK_B, SEL_HSCIF0_1),
        PINMUX_IPSR_MSEL(IP2_20_18, SPEEDIN, SEL_RSP_0),
-       PINMUX_IPSR_MSEL(IP2_20_18, VSP, SEL_SPDM_0),
        PINMUX_IPSR_MSEL(IP2_20_18, CAN_CLK_C, SEL_CAN_2),
        PINMUX_IPSR_GPSR(IP2_20_18, TPUTO2_B),
        PINMUX_IPSR_GPSR(IP2_23_21, A17),
        PINMUX_IPSR_MSEL(IP2_23_21, MSIOF2_SYNC, SEL_MSI2_0),
        PINMUX_IPSR_MSEL(IP2_23_21, SCIF4_RXD_E, SEL_SCIF4_4),
        PINMUX_IPSR_MSEL(IP2_23_21, CAN1_RX_B, SEL_CAN1_1),
-       PINMUX_IPSR_MSEL(IP2_23_21, AVB_AVTP_CAPTURE_B, SEL_AVB_1),
        PINMUX_IPSR_GPSR(IP2_26_24, A18),
        PINMUX_IPSR_MSEL(IP2_26_24, MSIOF2_SS1, SEL_MSI2_0),
        PINMUX_IPSR_MSEL(IP2_26_24, SCIF4_TXD_E, SEL_SCIF4_4),
        PINMUX_IPSR_MSEL(IP2_26_24, CAN1_TX_B, SEL_CAN1_1),
-       PINMUX_IPSR_MSEL(IP2_26_24, AVB_AVTP_MATCH_B, SEL_AVB_1),
        PINMUX_IPSR_GPSR(IP2_29_27, A19),
        PINMUX_IPSR_MSEL(IP2_29_27, MSIOF2_SS2, SEL_MSI2_0),
        PINMUX_IPSR_GPSR(IP2_29_27, PWM4),
        PINMUX_IPSR_GPSR(IP2_29_27, TPUTO2),
-       PINMUX_IPSR_GPSR(IP2_29_27, MOUT0),
        PINMUX_IPSR_GPSR(IP2_31_30, A20),
        PINMUX_IPSR_GPSR(IP2_31_30, SPCLK),
-       PINMUX_IPSR_GPSR(IP2_29_27, MOUT1),
 
        /* IPSR3 */
        PINMUX_IPSR_GPSR(IP3_1_0, A21),
        PINMUX_IPSR_GPSR(IP3_1_0, MOSI_IO0),
-       PINMUX_IPSR_GPSR(IP3_1_0, MOUT2),
        PINMUX_IPSR_GPSR(IP3_3_2, A22),
        PINMUX_IPSR_GPSR(IP3_3_2, MISO_IO1),
-       PINMUX_IPSR_GPSR(IP3_3_2, MOUT5),
        PINMUX_IPSR_GPSR(IP3_3_2, ATADIR1_N),
        PINMUX_IPSR_GPSR(IP3_5_4, A23),
        PINMUX_IPSR_GPSR(IP3_5_4, IO2),
-       PINMUX_IPSR_GPSR(IP3_5_4, MOUT6),
        PINMUX_IPSR_GPSR(IP3_5_4, ATAWR1_N),
        PINMUX_IPSR_GPSR(IP3_7_6, A24),
        PINMUX_IPSR_GPSR(IP3_7_6, IO3),
@@ -815,40 +878,31 @@ static const u16 pinmux_data[] = {
        PINMUX_IPSR_GPSR(IP3_17_15, PWM0),
        PINMUX_IPSR_MSEL(IP3_17_15, SCIF4_RXD_C, SEL_SCIF4_2),
        PINMUX_IPSR_MSEL(IP3_17_15, TS_SDATA_B, SEL_TSIF0_1),
-       PINMUX_IPSR_MSEL(IP3_17_15, RIF0_SYNC, SEL_DR0_0),
        PINMUX_IPSR_GPSR(IP3_17_15, TPUTO3),
        PINMUX_IPSR_GPSR(IP3_17_15, SCIFB2_TXD),
-       PINMUX_IPSR_MSEL(IP3_17_15, SDATA_B, SEL_FSN_1),
        PINMUX_IPSR_GPSR(IP3_20_18, EX_CS3_N),
        PINMUX_IPSR_MSEL(IP3_20_18, SCIFA2_SCK, SEL_SCIFA2_0),
        PINMUX_IPSR_MSEL(IP3_20_18, SCIF4_TXD_C, SEL_SCIF4_2),
        PINMUX_IPSR_MSEL(IP3_20_18, TS_SCK_B, SEL_TSIF0_1),
-       PINMUX_IPSR_MSEL(IP3_20_18, RIF0_CLK, SEL_DR0_0),
        PINMUX_IPSR_MSEL(IP3_20_18, BPFCLK, SEL_DARC_0),
        PINMUX_IPSR_GPSR(IP3_20_18, SCIFB2_SCK),
-       PINMUX_IPSR_MSEL(IP3_20_18, MDATA_B, SEL_FSN_1),
        PINMUX_IPSR_GPSR(IP3_23_21, EX_CS4_N),
        PINMUX_IPSR_MSEL(IP3_23_21, SCIFA2_RXD, SEL_SCIFA2_0),
        PINMUX_IPSR_MSEL(IP3_23_21, I2C2_SCL_E, SEL_I2C02_4),
        PINMUX_IPSR_MSEL(IP3_23_21, TS_SDEN_B, SEL_TSIF0_1),
-       PINMUX_IPSR_MSEL(IP3_23_21, RIF0_D0, SEL_DR0_0),
        PINMUX_IPSR_MSEL(IP3_23_21, FMCLK, SEL_DARC_0),
        PINMUX_IPSR_GPSR(IP3_23_21, SCIFB2_CTS_N),
-       PINMUX_IPSR_MSEL(IP3_23_21, SCKZ_B, SEL_FSN_1),
        PINMUX_IPSR_GPSR(IP3_26_24, EX_CS5_N),
        PINMUX_IPSR_MSEL(IP3_26_24, SCIFA2_TXD, SEL_SCIFA2_0),
        PINMUX_IPSR_MSEL(IP3_26_24, I2C2_SDA_E, SEL_I2C02_4),
        PINMUX_IPSR_MSEL(IP3_26_24, TS_SPSYNC_B, SEL_TSIF0_1),
-       PINMUX_IPSR_MSEL(IP3_26_24, RIF0_D1, SEL_DR1_0),
        PINMUX_IPSR_MSEL(IP3_26_24, FMIN, SEL_DARC_0),
        PINMUX_IPSR_GPSR(IP3_26_24, SCIFB2_RTS_N),
-       PINMUX_IPSR_MSEL(IP3_26_24, STM_N_B, SEL_FSN_1),
        PINMUX_IPSR_GPSR(IP3_29_27, BS_N),
        PINMUX_IPSR_GPSR(IP3_29_27, DRACK0),
        PINMUX_IPSR_GPSR(IP3_29_27, PWM1_C),
        PINMUX_IPSR_GPSR(IP3_29_27, TPUTO0_C),
        PINMUX_IPSR_GPSR(IP3_29_27, ATACS01_N),
-       PINMUX_IPSR_MSEL(IP3_29_27, MTS_N_B, SEL_FSN_1),
        PINMUX_IPSR_GPSR(IP3_30, RD_N),
        PINMUX_IPSR_GPSR(IP3_30, ATACS11_N),
        PINMUX_IPSR_GPSR(IP3_31, RD_WR_N),
@@ -858,121 +912,88 @@ static const u16 pinmux_data[] = {
        PINMUX_IPSR_GPSR(IP4_1_0, EX_WAIT0),
        PINMUX_IPSR_MSEL(IP4_1_0, CAN_CLK_B, SEL_CAN_1),
        PINMUX_IPSR_MSEL(IP4_1_0, SCIF_CLK, SEL_SCIF0_0),
-       PINMUX_IPSR_GPSR(IP4_1_0, PWMFSW0),
        PINMUX_IPSR_GPSR(IP4_4_2, DU0_DR0),
        PINMUX_IPSR_GPSR(IP4_4_2, LCDOUT16),
        PINMUX_IPSR_MSEL(IP4_4_2, SCIF5_RXD_C, SEL_SCIF5_2),
        PINMUX_IPSR_MSEL(IP4_4_2, I2C2_SCL_D, SEL_I2C02_3),
-       PINMUX_IPSR_GPSR(IP4_4_2, CC50_STATE0),
        PINMUX_IPSR_GPSR(IP4_7_5, DU0_DR1),
        PINMUX_IPSR_GPSR(IP4_7_5, LCDOUT17),
        PINMUX_IPSR_MSEL(IP4_7_5, SCIF5_TXD_C, SEL_SCIF5_2),
        PINMUX_IPSR_MSEL(IP4_7_5, I2C2_SDA_D, SEL_I2C02_3),
-       PINMUX_IPSR_GPSR(IP4_9_8, CC50_STATE1),
        PINMUX_IPSR_GPSR(IP4_9_8, DU0_DR2),
        PINMUX_IPSR_GPSR(IP4_9_8, LCDOUT18),
-       PINMUX_IPSR_GPSR(IP4_9_8, CC50_STATE2),
        PINMUX_IPSR_GPSR(IP4_11_10, DU0_DR3),
        PINMUX_IPSR_GPSR(IP4_11_10, LCDOUT19),
-       PINMUX_IPSR_GPSR(IP4_11_10, CC50_STATE3),
        PINMUX_IPSR_GPSR(IP4_13_12, DU0_DR4),
        PINMUX_IPSR_GPSR(IP4_13_12, LCDOUT20),
-       PINMUX_IPSR_GPSR(IP4_13_12, CC50_STATE4),
        PINMUX_IPSR_GPSR(IP4_15_14, DU0_DR5),
        PINMUX_IPSR_GPSR(IP4_15_14, LCDOUT21),
-       PINMUX_IPSR_GPSR(IP4_15_14, CC50_STATE5),
        PINMUX_IPSR_GPSR(IP4_17_16, DU0_DR6),
        PINMUX_IPSR_GPSR(IP4_17_16, LCDOUT22),
-       PINMUX_IPSR_GPSR(IP4_17_16, CC50_STATE6),
        PINMUX_IPSR_GPSR(IP4_19_18, DU0_DR7),
        PINMUX_IPSR_GPSR(IP4_19_18, LCDOUT23),
-       PINMUX_IPSR_GPSR(IP4_19_18, CC50_STATE7),
        PINMUX_IPSR_GPSR(IP4_22_20, DU0_DG0),
        PINMUX_IPSR_GPSR(IP4_22_20, LCDOUT8),
        PINMUX_IPSR_MSEL(IP4_22_20, SCIFA0_RXD_C, SEL_SCIFA0_2),
        PINMUX_IPSR_MSEL(IP4_22_20, I2C3_SCL_D, SEL_I2C03_3),
-       PINMUX_IPSR_GPSR(IP4_22_20, CC50_STATE8),
        PINMUX_IPSR_GPSR(IP4_25_23, DU0_DG1),
        PINMUX_IPSR_GPSR(IP4_25_23, LCDOUT9),
        PINMUX_IPSR_MSEL(IP4_25_23, SCIFA0_TXD_C, SEL_SCIFA0_2),
        PINMUX_IPSR_MSEL(IP4_25_23, I2C3_SDA_D, SEL_I2C03_3),
-       PINMUX_IPSR_GPSR(IP4_25_23, CC50_STATE9),
        PINMUX_IPSR_GPSR(IP4_27_26, DU0_DG2),
        PINMUX_IPSR_GPSR(IP4_27_26, LCDOUT10),
-       PINMUX_IPSR_GPSR(IP4_27_26, CC50_STATE10),
        PINMUX_IPSR_GPSR(IP4_29_28, DU0_DG3),
        PINMUX_IPSR_GPSR(IP4_29_28, LCDOUT11),
-       PINMUX_IPSR_GPSR(IP4_29_28, CC50_STATE11),
        PINMUX_IPSR_GPSR(IP4_31_30, DU0_DG4),
        PINMUX_IPSR_GPSR(IP4_31_30, LCDOUT12),
-       PINMUX_IPSR_GPSR(IP4_31_30, CC50_STATE12),
 
        /* IPSR5 */
        PINMUX_IPSR_GPSR(IP5_1_0, DU0_DG5),
        PINMUX_IPSR_GPSR(IP5_1_0, LCDOUT13),
-       PINMUX_IPSR_GPSR(IP5_1_0, CC50_STATE13),
        PINMUX_IPSR_GPSR(IP5_3_2, DU0_DG6),
        PINMUX_IPSR_GPSR(IP5_3_2, LCDOUT14),
-       PINMUX_IPSR_GPSR(IP5_3_2, CC50_STATE14),
        PINMUX_IPSR_GPSR(IP5_5_4, DU0_DG7),
        PINMUX_IPSR_GPSR(IP5_5_4, LCDOUT15),
-       PINMUX_IPSR_GPSR(IP5_5_4, CC50_STATE15),
        PINMUX_IPSR_GPSR(IP5_8_6, DU0_DB0),
        PINMUX_IPSR_GPSR(IP5_8_6, LCDOUT0),
        PINMUX_IPSR_MSEL(IP5_8_6, SCIFA4_RXD_C, SEL_SCIFA4_2),
        PINMUX_IPSR_MSEL(IP5_8_6, I2C4_SCL_D, SEL_I2C04_3),
        PINMUX_IPSR_MSEL(IP7_8_6, CAN0_RX_C, SEL_CAN0_2),
-       PINMUX_IPSR_GPSR(IP5_8_6, CC50_STATE16),
        PINMUX_IPSR_GPSR(IP5_11_9, DU0_DB1),
        PINMUX_IPSR_GPSR(IP5_11_9, LCDOUT1),
        PINMUX_IPSR_MSEL(IP5_11_9, SCIFA4_TXD_C, SEL_SCIFA4_2),
        PINMUX_IPSR_MSEL(IP5_11_9, I2C4_SDA_D, SEL_I2C04_3),
        PINMUX_IPSR_MSEL(IP5_11_9, CAN0_TX_C, SEL_CAN0_2),
-       PINMUX_IPSR_GPSR(IP5_11_9, CC50_STATE17),
        PINMUX_IPSR_GPSR(IP5_13_12, DU0_DB2),
        PINMUX_IPSR_GPSR(IP5_13_12, LCDOUT2),
-       PINMUX_IPSR_GPSR(IP5_13_12, CC50_STATE18),
        PINMUX_IPSR_GPSR(IP5_15_14, DU0_DB3),
        PINMUX_IPSR_GPSR(IP5_15_14, LCDOUT3),
-       PINMUX_IPSR_GPSR(IP5_15_14, CC50_STATE19),
        PINMUX_IPSR_GPSR(IP5_17_16, DU0_DB4),
        PINMUX_IPSR_GPSR(IP5_17_16, LCDOUT4),
-       PINMUX_IPSR_GPSR(IP5_17_16, CC50_STATE20),
        PINMUX_IPSR_GPSR(IP5_19_18, DU0_DB5),
        PINMUX_IPSR_GPSR(IP5_19_18, LCDOUT5),
-       PINMUX_IPSR_GPSR(IP5_19_18, CC50_STATE21),
        PINMUX_IPSR_GPSR(IP5_21_20, DU0_DB6),
        PINMUX_IPSR_GPSR(IP5_21_20, LCDOUT6),
-       PINMUX_IPSR_GPSR(IP5_21_20, CC50_STATE22),
        PINMUX_IPSR_GPSR(IP5_23_22, DU0_DB7),
        PINMUX_IPSR_GPSR(IP5_23_22, LCDOUT7),
-       PINMUX_IPSR_GPSR(IP5_23_22, CC50_STATE23),
        PINMUX_IPSR_GPSR(IP5_25_24, DU0_DOTCLKIN),
        PINMUX_IPSR_GPSR(IP5_25_24, QSTVA_QVS),
-       PINMUX_IPSR_GPSR(IP5_25_24, CC50_STATE24),
        PINMUX_IPSR_GPSR(IP5_27_26, DU0_DOTCLKOUT0),
        PINMUX_IPSR_GPSR(IP5_27_26, QCLK),
-       PINMUX_IPSR_GPSR(IP5_27_26, CC50_STATE25),
        PINMUX_IPSR_GPSR(IP5_29_28, DU0_DOTCLKOUT1),
        PINMUX_IPSR_GPSR(IP5_29_28, QSTVB_QVE),
-       PINMUX_IPSR_GPSR(IP5_29_28, CC50_STATE26),
        PINMUX_IPSR_GPSR(IP5_31_30, DU0_EXHSYNC_DU0_HSYNC),
        PINMUX_IPSR_GPSR(IP5_31_30, QSTH_QHS),
-       PINMUX_IPSR_GPSR(IP5_31_30, CC50_STATE27),
 
        /* IPSR6 */
        PINMUX_IPSR_GPSR(IP6_1_0, DU0_EXVSYNC_DU0_VSYNC),
        PINMUX_IPSR_GPSR(IP6_1_0, QSTB_QHE),
-       PINMUX_IPSR_GPSR(IP6_1_0, CC50_STATE28),
        PINMUX_IPSR_GPSR(IP6_3_2, DU0_EXODDF_DU0_ODDF_DISP_CDE),
        PINMUX_IPSR_GPSR(IP6_3_2, QCPV_QDE),
-       PINMUX_IPSR_GPSR(IP6_3_2, CC50_STATE29),
        PINMUX_IPSR_GPSR(IP6_5_4, DU0_DISP),
        PINMUX_IPSR_GPSR(IP6_5_4, QPOLA),
-       PINMUX_IPSR_GPSR(IP6_5_4, CC50_STATE30),
        PINMUX_IPSR_GPSR(IP6_7_6, DU0_CDE),
        PINMUX_IPSR_GPSR(IP6_7_6, QPOLB),
-       PINMUX_IPSR_GPSR(IP6_7_6, CC50_STATE31),
        PINMUX_IPSR_GPSR(IP6_8, VI0_CLK),
        PINMUX_IPSR_GPSR(IP6_8, AVB_RX_CLK),
        PINMUX_IPSR_GPSR(IP6_9, VI0_DATA0_VI0_B0),
@@ -1017,7 +1038,6 @@ static const u16 pinmux_data[] = {
        PINMUX_IPSR_MSEL(IP6_31_29, I2C5_SCL_D, SEL_I2C05_3),
        PINMUX_IPSR_GPSR(IP6_31_29, AVB_TX_CLK),
        PINMUX_IPSR_MSEL(IP6_31_29, ADIDATA, SEL_RAD_0),
-       PINMUX_IPSR_MSEL(IP6_31_29, AD_DI, SEL_ADI_0),
 
        /* IPSR7 */
        PINMUX_IPSR_MSEL(IP7_2_0, ETH_CRS_DV, SEL_ETH_0),
@@ -1026,21 +1046,18 @@ static const u16 pinmux_data[] = {
        PINMUX_IPSR_MSEL(IP7_2_0, I2C5_SDA_D, SEL_I2C05_3),
        PINMUX_IPSR_GPSR(IP7_2_0, AVB_TXD0),
        PINMUX_IPSR_MSEL(IP7_2_0, ADICS_SAMP, SEL_RAD_0),
-       PINMUX_IPSR_MSEL(IP7_2_0, AD_DO, SEL_ADI_0),
        PINMUX_IPSR_MSEL(IP7_5_3, ETH_RX_ER, SEL_ETH_0),
        PINMUX_IPSR_GPSR(IP7_5_3, VI0_G2),
        PINMUX_IPSR_MSEL(IP7_5_3, MSIOF2_SCK_B, SEL_MSI2_1),
        PINMUX_IPSR_MSEL(IP7_5_3, CAN0_RX_B, SEL_CAN0_1),
        PINMUX_IPSR_GPSR(IP7_5_3, AVB_TXD1),
        PINMUX_IPSR_MSEL(IP7_5_3, ADICLK, SEL_RAD_0),
-       PINMUX_IPSR_MSEL(IP7_5_3, AD_CLK, SEL_ADI_0),
        PINMUX_IPSR_MSEL(IP7_8_6, ETH_RXD0, SEL_ETH_0),
        PINMUX_IPSR_GPSR(IP7_8_6, VI0_G3),
        PINMUX_IPSR_MSEL(IP7_8_6, MSIOF2_SYNC_B, SEL_MSI2_1),
        PINMUX_IPSR_MSEL(IP7_8_6, CAN0_TX_B, SEL_CAN0_1),
        PINMUX_IPSR_GPSR(IP7_8_6, AVB_TXD2),
        PINMUX_IPSR_MSEL(IP7_8_6, ADICHS0, SEL_RAD_0),
-       PINMUX_IPSR_MSEL(IP7_8_6, AD_NCS_N, SEL_ADI_0),
        PINMUX_IPSR_MSEL(IP7_11_9, ETH_RXD1, SEL_ETH_0),
        PINMUX_IPSR_GPSR(IP7_11_9, VI0_G4),
        PINMUX_IPSR_MSEL(IP7_11_9, MSIOF2_SS1_B, SEL_MSI2_1),
@@ -1136,60 +1153,48 @@ static const u16 pinmux_data[] = {
        PINMUX_IPSR_MSEL(IP8_25_23, SCIF4_RXD, SEL_SCIF4_0),
        PINMUX_IPSR_GPSR(IP8_25_23, PWM5_B),
        PINMUX_IPSR_GPSR(IP8_25_23, DU1_DR0),
-       PINMUX_IPSR_MSEL(IP8_25_23, RIF1_SYNC_B, SEL_DR2_1),
        PINMUX_IPSR_MSEL(IP8_25_23, TS_SDATA_D, SEL_TSIF0_3),
        PINMUX_IPSR_GPSR(IP8_25_23, TPUTO1_B),
        PINMUX_IPSR_MSEL(IP8_28_26, I2C1_SDA, SEL_I2C01_0),
        PINMUX_IPSR_MSEL(IP8_28_26, SCIF4_TXD, SEL_SCIF4_0),
        PINMUX_IPSR_GPSR(IP8_28_26, IRQ5),
        PINMUX_IPSR_GPSR(IP8_28_26, DU1_DR1),
-       PINMUX_IPSR_MSEL(IP8_28_26, RIF1_CLK_B, SEL_DR2_1),
        PINMUX_IPSR_MSEL(IP8_28_26, TS_SCK_D, SEL_TSIF0_3),
        PINMUX_IPSR_MSEL(IP8_28_26, BPFCLK_C, SEL_DARC_2),
        PINMUX_IPSR_GPSR(IP8_31_29, MSIOF0_RXD),
        PINMUX_IPSR_MSEL(IP8_31_29, SCIF5_RXD, SEL_SCIF5_0),
        PINMUX_IPSR_MSEL(IP8_31_29, I2C2_SCL_C, SEL_I2C02_2),
        PINMUX_IPSR_GPSR(IP8_31_29, DU1_DR2),
-       PINMUX_IPSR_MSEL(IP8_31_29, RIF1_D0_B, SEL_DR2_1),
        PINMUX_IPSR_MSEL(IP8_31_29, TS_SDEN_D, SEL_TSIF0_3),
        PINMUX_IPSR_MSEL(IP8_31_29, FMCLK_C, SEL_DARC_2),
-       PINMUX_IPSR_MSEL(IP8_31_29, RDS_CLK, SEL_RDS_0),
 
        /* IPSR9 */
        PINMUX_IPSR_GPSR(IP9_2_0, MSIOF0_TXD),
        PINMUX_IPSR_MSEL(IP9_2_0, SCIF5_TXD, SEL_SCIF5_0),
        PINMUX_IPSR_MSEL(IP9_2_0, I2C2_SDA_C, SEL_I2C02_2),
        PINMUX_IPSR_GPSR(IP9_2_0, DU1_DR3),
-       PINMUX_IPSR_MSEL(IP9_2_0, RIF1_D1_B, SEL_DR3_1),
        PINMUX_IPSR_MSEL(IP9_2_0, TS_SPSYNC_D, SEL_TSIF0_3),
        PINMUX_IPSR_MSEL(IP9_2_0, FMIN_C, SEL_DARC_2),
-       PINMUX_IPSR_MSEL(IP9_2_0, RDS_DATA, SEL_RDS_0),
        PINMUX_IPSR_GPSR(IP9_5_3, MSIOF0_SCK),
        PINMUX_IPSR_GPSR(IP9_5_3, IRQ0),
        PINMUX_IPSR_MSEL(IP9_5_3, TS_SDATA, SEL_TSIF0_0),
        PINMUX_IPSR_GPSR(IP9_5_3, DU1_DR4),
-       PINMUX_IPSR_MSEL(IP9_5_3, RIF1_SYNC, SEL_DR2_0),
        PINMUX_IPSR_GPSR(IP9_5_3, TPUTO1_C),
        PINMUX_IPSR_GPSR(IP9_8_6, MSIOF0_SYNC),
        PINMUX_IPSR_GPSR(IP9_8_6, PWM1),
        PINMUX_IPSR_MSEL(IP9_8_6, TS_SCK, SEL_TSIF0_0),
        PINMUX_IPSR_GPSR(IP9_8_6, DU1_DR5),
-       PINMUX_IPSR_MSEL(IP9_8_6, RIF1_CLK, SEL_DR2_0),
        PINMUX_IPSR_MSEL(IP9_8_6, BPFCLK_B, SEL_DARC_1),
        PINMUX_IPSR_GPSR(IP9_11_9, MSIOF0_SS1),
        PINMUX_IPSR_MSEL(IP9_11_9, SCIFA0_RXD, SEL_SCIFA0_0),
        PINMUX_IPSR_MSEL(IP9_11_9, TS_SDEN, SEL_TSIF0_0),
        PINMUX_IPSR_GPSR(IP9_11_9, DU1_DR6),
-       PINMUX_IPSR_MSEL(IP9_11_9, RIF1_D0, SEL_DR2_0),
        PINMUX_IPSR_MSEL(IP9_11_9, FMCLK_B, SEL_DARC_1),
-       PINMUX_IPSR_MSEL(IP9_11_9, RDS_CLK_B, SEL_RDS_1),
        PINMUX_IPSR_GPSR(IP9_14_12, MSIOF0_SS2),
        PINMUX_IPSR_MSEL(IP9_14_12, SCIFA0_TXD, SEL_SCIFA0_0),
        PINMUX_IPSR_MSEL(IP9_14_12, TS_SPSYNC, SEL_TSIF0_0),
        PINMUX_IPSR_GPSR(IP9_14_12, DU1_DR7),
-       PINMUX_IPSR_MSEL(IP9_14_12, RIF1_D1, SEL_DR3_0),
        PINMUX_IPSR_MSEL(IP9_14_12, FMIN_B, SEL_DARC_1),
-       PINMUX_IPSR_MSEL(IP9_14_12, RDS_DATA_B, SEL_RDS_1),
        PINMUX_IPSR_MSEL(IP9_16_15, HSCIF1_HRX, SEL_HSCIF1_0),
        PINMUX_IPSR_MSEL(IP9_16_15, I2C4_SCL, SEL_I2C04_0),
        PINMUX_IPSR_GPSR(IP9_16_15, PWM6),
@@ -1204,128 +1209,93 @@ static const u16 pinmux_data[] = {
        PINMUX_IPSR_GPSR(IP9_21_19, DU1_DG2),
        PINMUX_IPSR_MSEL(IP9_21_19, REMOCON_B, SEL_RCN_1),
        PINMUX_IPSR_MSEL(IP9_21_19, SPEEDIN_B, SEL_RSP_1),
-       PINMUX_IPSR_MSEL(IP9_21_19, VSP_B, SEL_SPDM_1),
        PINMUX_IPSR_MSEL(IP9_24_22, HSCIF1_HCTS_N, SEL_HSCIF1_0),
        PINMUX_IPSR_MSEL(IP9_24_22, SCIFA4_RXD, SEL_SCIFA4_0),
        PINMUX_IPSR_MSEL(IP9_24_22, IECLK, SEL_IEB_0),
        PINMUX_IPSR_GPSR(IP9_24_22, DU1_DG3),
        PINMUX_IPSR_MSEL(IP9_24_22, SSI_SCK1_B, SEL_SSI1_1),
-       PINMUX_IPSR_GPSR(IP9_24_22, CAN_DEBUG_HW_TRIGGER),
-       PINMUX_IPSR_GPSR(IP9_24_22, CC50_STATE32),
        PINMUX_IPSR_MSEL(IP9_27_25, HSCIF1_HRTS_N, SEL_HSCIF1_0),
        PINMUX_IPSR_MSEL(IP9_27_25, SCIFA4_TXD, SEL_SCIFA4_0),
        PINMUX_IPSR_MSEL(IP9_27_25, IERX, SEL_IEB_0),
        PINMUX_IPSR_GPSR(IP9_27_25, DU1_DG4),
        PINMUX_IPSR_MSEL(IP9_27_25, SSI_WS1_B, SEL_SSI1_1),
-       PINMUX_IPSR_GPSR(IP9_27_25, CAN_STEP0),
-       PINMUX_IPSR_GPSR(IP9_27_25, CC50_STATE33),
        PINMUX_IPSR_MSEL(IP9_30_28, SCIF1_SCK, SEL_SCIF1_0),
        PINMUX_IPSR_GPSR(IP9_30_28, PWM3),
        PINMUX_IPSR_MSEL(IP9_30_28, TCLK2, SEL_TMU_0),
        PINMUX_IPSR_GPSR(IP9_30_28, DU1_DG5),
        PINMUX_IPSR_MSEL(IP9_30_28, SSI_SDATA1_B, SEL_SSI1_1),
-       PINMUX_IPSR_GPSR(IP9_30_28, CAN_TXCLK),
-       PINMUX_IPSR_GPSR(IP9_30_28, CC50_STATE34),
 
        /* IPSR10 */
        PINMUX_IPSR_MSEL(IP10_2_0, SCIF1_RXD, SEL_SCIF1_0),
        PINMUX_IPSR_MSEL(IP10_2_0, I2C5_SCL, SEL_I2C05_0),
        PINMUX_IPSR_GPSR(IP10_2_0, DU1_DG6),
        PINMUX_IPSR_MSEL(IP10_2_0, SSI_SCK2_B, SEL_SSI2_1),
-       PINMUX_IPSR_GPSR(IP10_2_0, CAN_DEBUGOUT0),
-       PINMUX_IPSR_GPSR(IP10_2_0, CC50_STATE35),
        PINMUX_IPSR_MSEL(IP10_5_3, SCIF1_TXD, SEL_SCIF1_0),
        PINMUX_IPSR_MSEL(IP10_5_3, I2C5_SDA, SEL_I2C05_0),
        PINMUX_IPSR_GPSR(IP10_5_3, DU1_DG7),
        PINMUX_IPSR_MSEL(IP10_5_3, SSI_WS2_B, SEL_SSI2_1),
-       PINMUX_IPSR_GPSR(IP10_5_3, CAN_DEBUGOUT1),
-       PINMUX_IPSR_GPSR(IP10_5_3, CC50_STATE36),
        PINMUX_IPSR_MSEL(IP10_8_6, SCIF2_RXD, SEL_SCIF2_0),
        PINMUX_IPSR_MSEL(IP10_8_6, IIC0_SCL, SEL_IIC0_0),
        PINMUX_IPSR_GPSR(IP10_8_6, DU1_DB0),
        PINMUX_IPSR_MSEL(IP10_8_6, SSI_SDATA2_B, SEL_SSI2_1),
-       PINMUX_IPSR_GPSR(IP10_8_6, USB0_EXTLP),
-       PINMUX_IPSR_GPSR(IP10_8_6, CAN_DEBUGOUT2),
-       PINMUX_IPSR_GPSR(IP10_8_6, CC50_STATE37),
        PINMUX_IPSR_MSEL(IP10_11_9, SCIF2_TXD, SEL_SCIF2_0),
        PINMUX_IPSR_MSEL(IP10_11_9, IIC0_SDA, SEL_IIC0_0),
        PINMUX_IPSR_GPSR(IP10_11_9, DU1_DB1),
        PINMUX_IPSR_MSEL(IP10_11_9, SSI_SCK9_B, SEL_SSI9_1),
-       PINMUX_IPSR_GPSR(IP10_11_9, USB0_OVC1),
-       PINMUX_IPSR_GPSR(IP10_11_9, CAN_DEBUGOUT3),
-       PINMUX_IPSR_GPSR(IP10_11_9, CC50_STATE38),
        PINMUX_IPSR_MSEL(IP10_14_12, SCIF2_SCK, SEL_SCIF2_0),
        PINMUX_IPSR_GPSR(IP10_14_12, IRQ1),
        PINMUX_IPSR_GPSR(IP10_14_12, DU1_DB2),
        PINMUX_IPSR_MSEL(IP10_14_12, SSI_WS9_B, SEL_SSI9_1),
-       PINMUX_IPSR_GPSR(IP10_14_12, USB0_IDIN),
-       PINMUX_IPSR_GPSR(IP10_14_12, CAN_DEBUGOUT4),
-       PINMUX_IPSR_GPSR(IP10_14_12, CC50_STATE39),
        PINMUX_IPSR_MSEL(IP10_17_15, SCIF3_SCK, SEL_SCIF3_0),
        PINMUX_IPSR_GPSR(IP10_17_15, IRQ2),
        PINMUX_IPSR_MSEL(IP10_17_15, BPFCLK_D, SEL_DARC_3),
        PINMUX_IPSR_GPSR(IP10_17_15, DU1_DB3),
        PINMUX_IPSR_MSEL(IP10_17_15, SSI_SDATA9_B, SEL_SSI9_1),
-       PINMUX_IPSR_GPSR(IP10_17_15, TANS2),
-       PINMUX_IPSR_GPSR(IP10_17_15, CAN_DEBUGOUT5),
-       PINMUX_IPSR_GPSR(IP10_17_15, CC50_OSCOUT),
        PINMUX_IPSR_MSEL(IP10_20_18, SCIF3_RXD, SEL_SCIF3_0),
        PINMUX_IPSR_MSEL(IP10_20_18, I2C1_SCL_E, SEL_I2C01_4),
        PINMUX_IPSR_MSEL(IP10_20_18, FMCLK_D, SEL_DARC_3),
        PINMUX_IPSR_GPSR(IP10_20_18, DU1_DB4),
        PINMUX_IPSR_MSEL(IP10_20_18, AUDIO_CLKA_C, SEL_ADG_2),
        PINMUX_IPSR_MSEL(IP10_20_18, SSI_SCK4_B, SEL_SSI4_1),
-       PINMUX_IPSR_GPSR(IP10_20_18, CAN_DEBUGOUT6),
-       PINMUX_IPSR_MSEL(IP10_20_18, RDS_CLK_C, SEL_RDS_2),
        PINMUX_IPSR_MSEL(IP10_23_21, SCIF3_TXD, SEL_SCIF3_0),
        PINMUX_IPSR_MSEL(IP10_23_21, I2C1_SDA_E, SEL_I2C01_4),
        PINMUX_IPSR_MSEL(IP10_23_21, FMIN_D, SEL_DARC_3),
        PINMUX_IPSR_GPSR(IP10_23_21, DU1_DB5),
        PINMUX_IPSR_MSEL(IP10_23_21, AUDIO_CLKB_C, SEL_ADG_2),
        PINMUX_IPSR_MSEL(IP10_23_21, SSI_WS4_B, SEL_SSI4_1),
-       PINMUX_IPSR_GPSR(IP10_23_21, CAN_DEBUGOUT7),
-       PINMUX_IPSR_MSEL(IP10_23_21, RDS_DATA_C, SEL_RDS_2),
        PINMUX_IPSR_MSEL(IP10_26_24, I2C2_SCL, SEL_I2C02_0),
        PINMUX_IPSR_MSEL(IP10_26_24, SCIFA5_RXD, SEL_SCIFA5_0),
        PINMUX_IPSR_GPSR(IP10_26_24, DU1_DB6),
        PINMUX_IPSR_MSEL(IP10_26_24, AUDIO_CLKC_C, SEL_ADG_2),
        PINMUX_IPSR_MSEL(IP10_26_24, SSI_SDATA4_B, SEL_SSI4_1),
-       PINMUX_IPSR_GPSR(IP10_26_24, CAN_DEBUGOUT8),
        PINMUX_IPSR_MSEL(IP10_29_27, I2C2_SDA, SEL_I2C02_0),
        PINMUX_IPSR_MSEL(IP10_29_27, SCIFA5_TXD, SEL_SCIFA5_0),
        PINMUX_IPSR_GPSR(IP10_29_27, DU1_DB7),
        PINMUX_IPSR_MSEL(IP10_29_27, AUDIO_CLKOUT_C, SEL_ADG_2),
-       PINMUX_IPSR_GPSR(IP10_29_27, CAN_DEBUGOUT9),
        PINMUX_IPSR_MSEL(IP10_31_30, SSI_SCK5, SEL_SSI5_0),
        PINMUX_IPSR_MSEL(IP10_31_30, SCIFA3_SCK, SEL_SCIFA3_0),
        PINMUX_IPSR_GPSR(IP10_31_30, DU1_DOTCLKIN),
-       PINMUX_IPSR_GPSR(IP10_31_30, CAN_DEBUGOUT10),
 
        /* IPSR11 */
        PINMUX_IPSR_MSEL(IP11_2_0, SSI_WS5, SEL_SSI5_0),
        PINMUX_IPSR_MSEL(IP11_2_0, SCIFA3_RXD, SEL_SCIFA3_0),
        PINMUX_IPSR_MSEL(IP11_2_0, I2C3_SCL_C, SEL_I2C03_2),
        PINMUX_IPSR_GPSR(IP11_2_0, DU1_DOTCLKOUT0),
-       PINMUX_IPSR_GPSR(IP11_2_0, CAN_DEBUGOUT11),
        PINMUX_IPSR_MSEL(IP11_5_3, SSI_SDATA5, SEL_SSI5_0),
        PINMUX_IPSR_MSEL(IP11_5_3, SCIFA3_TXD, SEL_SCIFA3_0),
        PINMUX_IPSR_MSEL(IP11_5_3, I2C3_SDA_C, SEL_I2C03_2),
        PINMUX_IPSR_GPSR(IP11_5_3, DU1_DOTCLKOUT1),
-       PINMUX_IPSR_GPSR(IP11_5_3, CAN_DEBUGOUT12),
        PINMUX_IPSR_MSEL(IP11_7_6, SSI_SCK6, SEL_SSI6_0),
        PINMUX_IPSR_MSEL(IP11_7_6, SCIFA1_SCK_B, SEL_SCIFA1_1),
        PINMUX_IPSR_GPSR(IP11_7_6, DU1_EXHSYNC_DU1_HSYNC),
-       PINMUX_IPSR_GPSR(IP11_7_6, CAN_DEBUGOUT13),
        PINMUX_IPSR_MSEL(IP11_10_8, SSI_WS6, SEL_SSI6_0),
        PINMUX_IPSR_MSEL(IP11_10_8, SCIFA1_RXD_B, SEL_SCIFA1_1),
        PINMUX_IPSR_MSEL(IP11_10_8, I2C4_SCL_C, SEL_I2C04_2),
        PINMUX_IPSR_GPSR(IP11_10_8, DU1_EXVSYNC_DU1_VSYNC),
-       PINMUX_IPSR_GPSR(IP11_10_8, CAN_DEBUGOUT14),
        PINMUX_IPSR_MSEL(IP11_13_11, SSI_SDATA6, SEL_SSI6_0),
        PINMUX_IPSR_MSEL(IP11_13_11, SCIFA1_TXD_B, SEL_SCIFA1_1),
        PINMUX_IPSR_MSEL(IP11_13_11, I2C4_SDA_C, SEL_I2C04_2),
        PINMUX_IPSR_GPSR(IP11_13_11, DU1_EXODDF_DU1_ODDF_DISP_CDE),
-       PINMUX_IPSR_GPSR(IP11_13_11, CAN_DEBUGOUT15),
        PINMUX_IPSR_MSEL(IP11_15_14, SSI_SCK78, SEL_SSI7_0),
        PINMUX_IPSR_MSEL(IP11_15_14, SCIFA2_SCK_B, SEL_SCIFA2_1),
        PINMUX_IPSR_MSEL(IP11_15_14, I2C5_SDA_C, SEL_I2C05_2),
@@ -1339,30 +1309,24 @@ static const u16 pinmux_data[] = {
        PINMUX_IPSR_GPSR(IP11_20_18, IRQ8),
        PINMUX_IPSR_MSEL(IP11_20_18, AUDIO_CLKA_D, SEL_ADG_3),
        PINMUX_IPSR_MSEL(IP11_20_18, CAN_CLK_D, SEL_CAN_3),
-       PINMUX_IPSR_GPSR(IP11_20_18, PCMOE_N),
        PINMUX_IPSR_GPSR(IP11_23_21, SSI_SCK0129),
        PINMUX_IPSR_MSEL(IP11_23_21, MSIOF1_RXD_B, SEL_MSI1_1),
        PINMUX_IPSR_MSEL(IP11_23_21, SCIF5_RXD_D, SEL_SCIF5_3),
        PINMUX_IPSR_MSEL(IP11_23_21, ADIDATA_B, SEL_RAD_1),
-       PINMUX_IPSR_MSEL(IP11_23_21, AD_DI_B, SEL_ADI_1),
-       PINMUX_IPSR_GPSR(IP11_23_21, PCMWE_N),
        PINMUX_IPSR_GPSR(IP11_26_24, SSI_WS0129),
        PINMUX_IPSR_MSEL(IP11_26_24, MSIOF1_TXD_B, SEL_MSI1_1),
        PINMUX_IPSR_MSEL(IP11_26_24, SCIF5_TXD_D, SEL_SCIF5_3),
        PINMUX_IPSR_MSEL(IP11_26_24, ADICS_SAMP_B, SEL_RAD_1),
-       PINMUX_IPSR_MSEL(IP11_26_24, AD_DO_B, SEL_ADI_1),
        PINMUX_IPSR_GPSR(IP11_29_27, SSI_SDATA0),
        PINMUX_IPSR_MSEL(IP11_29_27, MSIOF1_SCK_B, SEL_MSI1_1),
        PINMUX_IPSR_GPSR(IP11_29_27, PWM0_B),
        PINMUX_IPSR_MSEL(IP11_29_27, ADICLK_B, SEL_RAD_1),
-       PINMUX_IPSR_MSEL(IP11_29_27, AD_CLK_B, SEL_ADI_1),
 
        /* IPSR12 */
        PINMUX_IPSR_GPSR(IP12_2_0, SSI_SCK34),
        PINMUX_IPSR_MSEL(IP12_2_0, MSIOF1_SYNC_B, SEL_MSI1_1),
        PINMUX_IPSR_MSEL(IP12_2_0, SCIFA1_SCK_C, SEL_SCIFA1_2),
        PINMUX_IPSR_MSEL(IP12_2_0, ADICHS0_B, SEL_RAD_1),
-       PINMUX_IPSR_MSEL(IP12_2_0, AD_NCS_N_B, SEL_ADI_1),
        PINMUX_IPSR_MSEL(IP12_2_0, DREQ1_N_B, SEL_LBS_1),
        PINMUX_IPSR_GPSR(IP12_5_3, SSI_WS34),
        PINMUX_IPSR_MSEL(IP12_5_3, MSIOF1_SS1_B, SEL_MSI1_1),
@@ -1379,15 +1343,12 @@ static const u16 pinmux_data[] = {
        PINMUX_IPSR_MSEL(IP12_10_9, SSI_SCK4, SEL_SSI4_0),
        PINMUX_IPSR_GPSR(IP12_10_9, MLB_CLK),
        PINMUX_IPSR_MSEL(IP12_10_9, IETX_B, SEL_IEB_1),
-       PINMUX_IPSR_GPSR(IP12_10_9, IRD_TX),
        PINMUX_IPSR_MSEL(IP12_12_11, SSI_WS4, SEL_SSI4_0),
        PINMUX_IPSR_GPSR(IP12_12_11, MLB_SIG),
        PINMUX_IPSR_MSEL(IP12_12_11, IECLK_B, SEL_IEB_1),
-       PINMUX_IPSR_GPSR(IP12_12_11, IRD_RX),
        PINMUX_IPSR_MSEL(IP12_14_13, SSI_SDATA4, SEL_SSI4_0),
        PINMUX_IPSR_GPSR(IP12_14_13, MLB_DAT),
        PINMUX_IPSR_MSEL(IP12_14_13, IERX_B, SEL_IEB_1),
-       PINMUX_IPSR_GPSR(IP12_14_13, IRD_SCK),
        PINMUX_IPSR_MSEL(IP12_17_15, SSI_SDATA8, SEL_SSI8_0),
        PINMUX_IPSR_MSEL(IP12_17_15, SCIF1_SCK_B, SEL_SCIF1_1),
        PINMUX_IPSR_GPSR(IP12_17_15, PWM1_B),
@@ -1400,25 +1361,21 @@ static const u16 pinmux_data[] = {
        PINMUX_IPSR_MSEL(IP12_20_18, IIC0_SCL_C, SEL_IIC0_2),
        PINMUX_IPSR_GPSR(IP12_20_18, VI1_CLK),
        PINMUX_IPSR_MSEL(IP12_20_18, CAN0_RX_D, SEL_CAN0_3),
-       PINMUX_IPSR_MSEL(IP12_20_18, AVB_AVTP_CAPTURE, SEL_AVB_0),
        PINMUX_IPSR_MSEL(IP12_20_18, ETH_CRS_DV_B, SEL_ETH_1),
        PINMUX_IPSR_MSEL(IP12_23_21, SSI_WS1, SEL_SSI1_0),
        PINMUX_IPSR_MSEL(IP12_23_21, SCIF1_TXD_B, SEL_SCIF1_1),
        PINMUX_IPSR_MSEL(IP12_23_21, IIC0_SDA_C, SEL_IIC0_2),
        PINMUX_IPSR_GPSR(IP12_23_21, VI1_DATA0),
        PINMUX_IPSR_MSEL(IP12_23_21, CAN0_TX_D, SEL_CAN0_3),
-       PINMUX_IPSR_MSEL(IP12_23_21, AVB_AVTP_MATCH, SEL_AVB_0),
        PINMUX_IPSR_MSEL(IP12_23_21, ETH_RX_ER_B, SEL_ETH_1),
        PINMUX_IPSR_MSEL(IP12_26_24, SSI_SDATA1, SEL_SSI1_0),
        PINMUX_IPSR_MSEL(IP12_26_24, HSCIF1_HRX_B, SEL_HSCIF1_1),
        PINMUX_IPSR_GPSR(IP12_26_24, VI1_DATA1),
-       PINMUX_IPSR_MSEL(IP12_26_24, SDATA, SEL_FSN_0),
        PINMUX_IPSR_GPSR(IP12_26_24, ATAWR0_N),
        PINMUX_IPSR_MSEL(IP12_26_24, ETH_RXD0_B, SEL_ETH_1),
        PINMUX_IPSR_MSEL(IP12_29_27, SSI_SCK2, SEL_SSI2_0),
        PINMUX_IPSR_MSEL(IP12_29_27, HSCIF1_HTX_B, SEL_HSCIF1_1),
        PINMUX_IPSR_GPSR(IP12_29_27, VI1_DATA2),
-       PINMUX_IPSR_MSEL(IP12_29_27, MDATA, SEL_FSN_0),
        PINMUX_IPSR_GPSR(IP12_29_27, ATAG0_N),
        PINMUX_IPSR_MSEL(IP12_29_27, ETH_RXD1_B, SEL_ETH_1),
 
@@ -1427,21 +1384,18 @@ static const u16 pinmux_data[] = {
        PINMUX_IPSR_MSEL(IP13_2_0, HSCIF1_HCTS_N_B, SEL_HSCIF1_1),
        PINMUX_IPSR_MSEL(IP13_2_0, SCIFA0_RXD_D, SEL_SCIFA0_3),
        PINMUX_IPSR_GPSR(IP13_2_0, VI1_DATA3),
-       PINMUX_IPSR_MSEL(IP13_2_0, SCKZ, SEL_FSN_0),
        PINMUX_IPSR_GPSR(IP13_2_0, ATACS00_N),
        PINMUX_IPSR_MSEL(IP13_2_0, ETH_LINK_B, SEL_ETH_1),
        PINMUX_IPSR_MSEL(IP13_5_3, SSI_SDATA2, SEL_SSI2_0),
        PINMUX_IPSR_MSEL(IP13_5_3, HSCIF1_HRTS_N_B, SEL_HSCIF1_1),
        PINMUX_IPSR_MSEL(IP13_5_3, SCIFA0_TXD_D, SEL_SCIFA0_3),
        PINMUX_IPSR_GPSR(IP13_5_3, VI1_DATA4),
-       PINMUX_IPSR_MSEL(IP13_5_3, STM_N, SEL_FSN_0),
        PINMUX_IPSR_GPSR(IP13_5_3, ATACS10_N),
        PINMUX_IPSR_MSEL(IP13_5_3, ETH_REFCLK_B, SEL_ETH_1),
        PINMUX_IPSR_MSEL(IP13_8_6, SSI_SCK9, SEL_SSI9_0),
        PINMUX_IPSR_MSEL(IP13_8_6, SCIF2_SCK_B, SEL_SCIF2_1),
        PINMUX_IPSR_GPSR(IP13_8_6, PWM2_B),
        PINMUX_IPSR_GPSR(IP13_8_6, VI1_DATA5),
-       PINMUX_IPSR_MSEL(IP13_8_6, MTS_N, SEL_FSN_0),
        PINMUX_IPSR_GPSR(IP13_8_6, EX_WAIT1),
        PINMUX_IPSR_MSEL(IP13_8_6, ETH_TXD1_B, SEL_ETH_1),
        PINMUX_IPSR_MSEL(IP13_11_9, SSI_WS9, SEL_SSI9_0),
@@ -1461,14 +1415,12 @@ static const u16 pinmux_data[] = {
        PINMUX_IPSR_MSEL(IP13_17_15, SCIFA4_RXD_D, SEL_SCIFA4_3),
        PINMUX_IPSR_GPSR(IP13_17_15, VI1_CLKENB),
        PINMUX_IPSR_MSEL(IP13_17_15, TS_SDATA_C, SEL_TSIF0_2),
-       PINMUX_IPSR_MSEL(IP13_17_15, RIF0_SYNC_B, SEL_DR0_1),
        PINMUX_IPSR_MSEL(IP13_17_15, ETH_TXD0_B, SEL_ETH_1),
        PINMUX_IPSR_MSEL(IP13_20_18, AUDIO_CLKB, SEL_ADG_0),
        PINMUX_IPSR_MSEL(IP13_20_18, I2C0_SDA_B, SEL_I2C00_1),
        PINMUX_IPSR_MSEL(IP13_20_18, SCIFA4_TXD_D, SEL_SCIFA4_3),
        PINMUX_IPSR_GPSR(IP13_20_18, VI1_FIELD),
        PINMUX_IPSR_MSEL(IP13_20_18, TS_SCK_C, SEL_TSIF0_2),
-       PINMUX_IPSR_MSEL(IP13_20_18, RIF0_CLK_B, SEL_DR0_1),
        PINMUX_IPSR_MSEL(IP13_20_18, BPFCLK_E, SEL_DARC_4),
        PINMUX_IPSR_MSEL(IP13_20_18, ETH_MDC_B, SEL_ETH_1),
        PINMUX_IPSR_MSEL(IP13_23_21, AUDIO_CLKC, SEL_ADG_0),
@@ -1476,17 +1428,13 @@ static const u16 pinmux_data[] = {
        PINMUX_IPSR_MSEL(IP13_23_21, SCIFA5_RXD_D, SEL_SCIFA5_3),
        PINMUX_IPSR_GPSR(IP13_23_21, VI1_HSYNC_N),
        PINMUX_IPSR_MSEL(IP13_23_21, TS_SDEN_C, SEL_TSIF0_2),
-       PINMUX_IPSR_MSEL(IP13_23_21, RIF0_D0_B, SEL_DR0_1),
        PINMUX_IPSR_MSEL(IP13_23_21, FMCLK_E, SEL_DARC_4),
-       PINMUX_IPSR_MSEL(IP13_23_21, RDS_CLK_D, SEL_RDS_3),
        PINMUX_IPSR_MSEL(IP13_26_24, AUDIO_CLKOUT, SEL_ADG_0),
        PINMUX_IPSR_MSEL(IP13_26_24, I2C4_SDA_B, SEL_I2C04_1),
        PINMUX_IPSR_MSEL(IP13_26_24, SCIFA5_TXD_D, SEL_SCIFA5_3),
        PINMUX_IPSR_GPSR(IP13_26_24, VI1_VSYNC_N),
        PINMUX_IPSR_MSEL(IP13_26_24, TS_SPSYNC_C, SEL_TSIF0_2),
-       PINMUX_IPSR_MSEL(IP13_26_24, RIF0_D1_B, SEL_DR1_1),
        PINMUX_IPSR_MSEL(IP13_26_24, FMIN_E, SEL_DARC_4),
-       PINMUX_IPSR_MSEL(IP13_26_24, RDS_DATA_D, SEL_RDS_3),
 };
 
 static const struct sh_pfc_pin pinmux_pins[] = {
@@ -4512,7 +4460,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                /* IP1_19_18 [2] */
                FN_D14, FN_SCIFA1_RXD, FN_I2C5_SCL_B, 0,
                /* IP1_17_15 [3] */
-               FN_D13, FN_SCIFA1_SCK, FN_TANS1, FN_PWM2_C, FN_TCLK2_B,
+               FN_D13, FN_SCIFA1_SCK, 0, FN_PWM2_C, FN_TCLK2_B,
                0, 0, 0,
                /* IP1_14_13 [2] */
                FN_D12, FN_HSCIF2_HRTS_N, FN_SCIF1_TXD_C, FN_I2C1_SDA_D,
@@ -4533,19 +4481,19 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
        { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
                             2, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2) {
                /* IP2_31_30 [2] */
-               FN_A20, FN_SPCLK, FN_MOUT1, 0,
+               FN_A20, FN_SPCLK, 0, 0,
                /* IP2_29_27 [3] */
                FN_A19, FN_MSIOF2_SS2, FN_PWM4, FN_TPUTO2,
-               FN_MOUT0, 0, 0, 0,
+               0, 0, 0, 0,
                /* IP2_26_24 [3] */
                FN_A18, FN_MSIOF2_SS1, FN_SCIF4_TXD_E, FN_CAN1_TX_B,
-               FN_AVB_AVTP_MATCH_B, 0, 0, 0,
+               0, 0, 0, 0,
                /* IP2_23_21 [3] */
                FN_A17, FN_MSIOF2_SYNC, FN_SCIF4_RXD_E, FN_CAN1_RX_B,
-               FN_AVB_AVTP_CAPTURE_B, 0, 0, 0,
+               0, 0, 0, 0,
                /* IP2_20_18 [3] */
                FN_A16, FN_MSIOF2_SCK, FN_HSCIF0_HSCK_B, FN_SPEEDIN,
-               FN_VSP, FN_CAN_CLK_C, FN_TPUTO2_B, 0,
+               0, FN_CAN_CLK_C, FN_TPUTO2_B, 0,
                /* IP2_17_16 [2] */
                FN_A15, FN_MSIOF2_TXD, FN_HSCIF0_HTX_B, FN_DACK1,
                /* IP2_15_14 [2] */
@@ -4573,19 +4521,19 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                FN_RD_N, FN_ATACS11_N,
                /* IP3_29_27 [3] */
                FN_BS_N, FN_DRACK0, FN_PWM1_C, FN_TPUTO0_C, FN_ATACS01_N,
-               FN_MTS_N_B, 0, 0,
+               0, 0, 0,
                /* IP3_26_24 [3] */
                FN_EX_CS5_N, FN_SCIFA2_TXD, FN_I2C2_SDA_E, FN_TS_SPSYNC_B,
-               FN_RIF0_D1, FN_FMIN, FN_SCIFB2_RTS_N, FN_STM_N_B,
+               0, FN_FMIN, FN_SCIFB2_RTS_N, 0,
                /* IP3_23_21 [3] */
                FN_EX_CS4_N, FN_SCIFA2_RXD, FN_I2C2_SCL_E, FN_TS_SDEN_B,
-               FN_RIF0_D0, FN_FMCLK, FN_SCIFB2_CTS_N, FN_SCKZ_B,
+               0, FN_FMCLK, FN_SCIFB2_CTS_N, 0,
                /* IP3_20_18 [3] */
                FN_EX_CS3_N, FN_SCIFA2_SCK, FN_SCIF4_TXD_C, FN_TS_SCK_B,
-               FN_RIF0_CLK, FN_BPFCLK, FN_SCIFB2_SCK, FN_MDATA_B,
+               0, FN_BPFCLK, FN_SCIFB2_SCK, 0,
                /* IP3_17_15 [3] */
                FN_EX_CS2_N, FN_PWM0, FN_SCIF4_RXD_C, FN_TS_SDATA_B,
-               FN_RIF0_SYNC, FN_TPUTO3, FN_SCIFB2_TXD, FN_SDATA_B,
+               0, FN_TPUTO3, FN_SCIFB2_TXD, 0,
                /* IP3_14_13 [2] */
                FN_EX_CS1_N, FN_TPUTO3_B, FN_SCIFB2_RXD, FN_VI1_DATA11,
                /* IP3_12 [1] */
@@ -4599,88 +4547,88 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                /* IP3_7_6 [2] */
                FN_A24, FN_IO3, FN_EX_WAIT2, 0,
                /* IP3_5_4 [2] */
-               FN_A23, FN_IO2, FN_MOUT6, FN_ATAWR1_N,
+               FN_A23, FN_IO2, 0, FN_ATAWR1_N,
                /* IP3_3_2 [2] */
-               FN_A22, FN_MISO_IO1, FN_MOUT5, FN_ATADIR1_N,
+               FN_A22, FN_MISO_IO1, 0, FN_ATADIR1_N,
                /* IP3_1_0 [2] */
-               FN_A21, FN_MOSI_IO0, FN_MOUT2, 0, }
+               FN_A21, FN_MOSI_IO0, 0, 0, }
        },
        { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
                             2, 2, 2, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 2) {
                /* IP4_31_30 [2] */
-               FN_DU0_DG4, FN_LCDOUT12, FN_CC50_STATE12, 0,
+               FN_DU0_DG4, FN_LCDOUT12, 0, 0,
                /* IP4_29_28 [2] */
-               FN_DU0_DG3, FN_LCDOUT11, FN_CC50_STATE11, 0,
+               FN_DU0_DG3, FN_LCDOUT11, 0, 0,
                /* IP4_27_26 [2] */
-               FN_DU0_DG2, FN_LCDOUT10, FN_CC50_STATE10, 0,
+               FN_DU0_DG2, FN_LCDOUT10, 0, 0,
                /* IP4_25_23 [3] */
                FN_DU0_DG1, FN_LCDOUT9, FN_SCIFA0_TXD_C, FN_I2C3_SDA_D,
-               FN_CC50_STATE9, 0, 0, 0,
+               0, 0, 0, 0,
                /* IP4_22_20 [3] */
                FN_DU0_DG0, FN_LCDOUT8, FN_SCIFA0_RXD_C, FN_I2C3_SCL_D,
-               FN_CC50_STATE8, 0, 0, 0,
+               0, 0, 0, 0,
                /* IP4_19_18 [2] */
-               FN_DU0_DR7, FN_LCDOUT23, FN_CC50_STATE7, 0,
+               FN_DU0_DR7, FN_LCDOUT23, 0, 0,
                /* IP4_17_16 [2] */
-               FN_DU0_DR6, FN_LCDOUT22, FN_CC50_STATE6, 0,
+               FN_DU0_DR6, FN_LCDOUT22, 0, 0,
                /* IP4_15_14 [2] */
-               FN_DU0_DR5, FN_LCDOUT21, FN_CC50_STATE5, 0,
+               FN_DU0_DR5, FN_LCDOUT21, 0, 0,
                /* IP4_13_12 [2] */
-               FN_DU0_DR4, FN_LCDOUT20, FN_CC50_STATE4, 0,
+               FN_DU0_DR4, FN_LCDOUT20, 0, 0,
                /* IP4_11_10 [2] */
-               FN_DU0_DR3, FN_LCDOUT19, FN_CC50_STATE3, 0,
+               FN_DU0_DR3, FN_LCDOUT19, 0, 0,
                /* IP4_9_8 [2] */
-               FN_DU0_DR2, FN_LCDOUT18, FN_CC50_STATE2, 0,
+               FN_DU0_DR2, FN_LCDOUT18, 0, 0,
                /* IP4_7_5 [3] */
                FN_DU0_DR1, FN_LCDOUT17, FN_SCIF5_TXD_C, FN_I2C2_SDA_D,
-               FN_CC50_STATE1, 0, 0, 0,
+               0, 0, 0, 0,
                /* IP4_4_2 [3] */
                FN_DU0_DR0, FN_LCDOUT16, FN_SCIF5_RXD_C, FN_I2C2_SCL_D,
-               FN_CC50_STATE0, 0, 0, 0,
+               0, 0, 0, 0,
                /* IP4_1_0 [2] */
-               FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK, FN_PWMFSW0, }
+               FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK, 0, }
        },
        { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
                             2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 2, 2, 2) {
                /* IP5_31_30 [2] */
-               FN_DU0_EXHSYNC_DU0_HSYNC, FN_QSTH_QHS, FN_CC50_STATE27, 0,
+               FN_DU0_EXHSYNC_DU0_HSYNC, FN_QSTH_QHS, 0, 0,
                /* IP5_29_28 [2] */
-               FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE, FN_CC50_STATE26, 0,
+               FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE, 0, 0,
                /* IP5_27_26 [2] */
-               FN_DU0_DOTCLKOUT0, FN_QCLK, FN_CC50_STATE25, 0,
+               FN_DU0_DOTCLKOUT0, FN_QCLK, 0, 0,
                /* IP5_25_24 [2] */
-               FN_DU0_DOTCLKIN, FN_QSTVA_QVS, FN_CC50_STATE24, 0,
+               FN_DU0_DOTCLKIN, FN_QSTVA_QVS, 0, 0,
                /* IP5_23_22 [2] */
-               FN_DU0_DB7, FN_LCDOUT7, FN_CC50_STATE23, 0,
+               FN_DU0_DB7, FN_LCDOUT7, 0, 0,
                /* IP5_21_20 [2] */
-               FN_DU0_DB6, FN_LCDOUT6, FN_CC50_STATE22, 0,
+               FN_DU0_DB6, FN_LCDOUT6, 0, 0,
                /* IP5_19_18 [2] */
-               FN_DU0_DB5, FN_LCDOUT5, FN_CC50_STATE21, 0,
+               FN_DU0_DB5, FN_LCDOUT5, 0, 0,
                /* IP5_17_16 [2] */
-               FN_DU0_DB4, FN_LCDOUT4, FN_CC50_STATE20, 0,
+               FN_DU0_DB4, FN_LCDOUT4, 0, 0,
                /* IP5_15_14 [2] */
-               FN_DU0_DB3, FN_LCDOUT3, FN_CC50_STATE19, 0,
+               FN_DU0_DB3, FN_LCDOUT3, 0, 0,
                /* IP5_13_12 [2] */
-               FN_DU0_DB2, FN_LCDOUT2, FN_CC50_STATE18, 0,
+               FN_DU0_DB2, FN_LCDOUT2, 0, 0,
                /* IP5_11_9 [3] */
                FN_DU0_DB1, FN_LCDOUT1, FN_SCIFA4_TXD_C, FN_I2C4_SDA_D,
-               FN_CAN0_TX_C, FN_CC50_STATE17, 0, 0,
+               FN_CAN0_TX_C, 0, 0, 0,
                /* IP5_8_6 [3] */
                FN_DU0_DB0, FN_LCDOUT0, FN_SCIFA4_RXD_C, FN_I2C4_SCL_D,
-               FN_CAN0_RX_C, FN_CC50_STATE16, 0, 0,
+               FN_CAN0_RX_C, 0, 0, 0,
                /* IP5_5_4 [2] */
-               FN_DU0_DG7, FN_LCDOUT15, FN_CC50_STATE15, 0,
+               FN_DU0_DG7, FN_LCDOUT15, 0, 0,
                /* IP5_3_2 [2] */
-               FN_DU0_DG6, FN_LCDOUT14, FN_CC50_STATE14, 0,
+               FN_DU0_DG6, FN_LCDOUT14, 0, 0,
                /* IP5_1_0 [2] */
-               FN_DU0_DG5, FN_LCDOUT13, FN_CC50_STATE13, 0, }
+               FN_DU0_DG5, FN_LCDOUT13, 0, 0, }
        },
        { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
                             3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2,
                             2, 2) {
                /* IP6_31_29 [3] */
                FN_ETH_MDIO, FN_VI0_G0, FN_MSIOF2_RXD_B, FN_I2C5_SCL_D,
-               FN_AVB_TX_CLK, FN_ADIDATA, FN_AD_DI, 0,
+               FN_AVB_TX_CLK, FN_ADIDATA, 0, 0,
                /* IP6_28_26 [3] */
                FN_VI0_VSYNC_N, FN_SCIF0_TXD_B, FN_I2C0_SDA_C,
                FN_AUDIO_CLKOUT_B, FN_AVB_TX_EN, 0, 0, 0,
@@ -4712,14 +4660,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                /* IP6_8 [1] */
                FN_VI0_CLK, FN_AVB_RX_CLK,
                /* IP6_7_6 [2] */
-               FN_DU0_CDE, FN_QPOLB, FN_CC50_STATE31, 0,
+               FN_DU0_CDE, FN_QPOLB, 0, 0,
                /* IP6_5_4 [2] */
-               FN_DU0_DISP, FN_QPOLA, FN_CC50_STATE30, 0,
+               FN_DU0_DISP, FN_QPOLA, 0, 0,
                /* IP6_3_2 [2] */
-               FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, FN_CC50_STATE29,
+               FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, 0,
                0,
                /* IP6_1_0 [2] */
-               FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, FN_CC50_STATE28, 0, }
+               FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, 0, 0, }
        },
        { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
                             1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
@@ -4750,25 +4698,25 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                FN_AVB_TXD3, FN_ADICHS1, 0, 0,
                /* IP7_8_6 [3] */
                FN_ETH_RXD0, FN_VI0_G3, FN_MSIOF2_SYNC_B, FN_CAN0_TX_B,
-               FN_AVB_TXD2, FN_ADICHS0, FN_AD_NCS_N, 0,
+               FN_AVB_TXD2, FN_ADICHS0, 0, 0,
                /* IP7_5_3 [3] */
                FN_ETH_RX_ER, FN_VI0_G2, FN_MSIOF2_SCK_B, FN_CAN0_RX_B,
-               FN_AVB_TXD1, FN_ADICLK, FN_AD_CLK, 0,
+               FN_AVB_TXD1, FN_ADICLK, 0, 0,
                /* IP7_2_0 [3] */
                FN_ETH_CRS_DV, FN_VI0_G1, FN_MSIOF2_TXD_B, FN_I2C5_SDA_D,
-               FN_AVB_TXD0, FN_ADICS_SAMP, FN_AD_DO, 0, }
+               FN_AVB_TXD0, FN_ADICS_SAMP, 0, 0, }
        },
        { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
                             3, 3, 3, 3, 3, 2, 3, 3, 3, 3, 3) {
                /* IP8_31_29 [3] */
                FN_MSIOF0_RXD, FN_SCIF5_RXD, FN_I2C2_SCL_C, FN_DU1_DR2,
-               FN_RIF1_D0_B, FN_TS_SDEN_D, FN_FMCLK_C, FN_RDS_CLK,
+               0, FN_TS_SDEN_D, FN_FMCLK_C, 0,
                /* IP8_28_26 [3] */
                FN_I2C1_SDA, FN_SCIF4_TXD, FN_IRQ5, FN_DU1_DR1,
-               FN_RIF1_CLK_B, FN_TS_SCK_D, FN_BPFCLK_C, 0,
+               0, FN_TS_SCK_D, FN_BPFCLK_C, 0,
                /* IP8_25_23 [3] */
                FN_I2C1_SCL, FN_SCIF4_RXD, FN_PWM5_B, FN_DU1_DR0,
-               FN_RIF1_SYNC_B, FN_TS_SDATA_D, FN_TPUTO1_B, 0,
+               0, FN_TS_SDATA_D, FN_TPUTO1_B, 0,
                /* IP8_22_20 [3] */
                FN_I2C0_SDA, FN_SCIF0_TXD_C, FN_TPUTO0, FN_CAN_CLK,
                FN_DVC_MUTE, FN_CAN1_TX_D, 0, 0,
@@ -4799,70 +4747,70 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                0, 0,
                /* IP9_30_28 [3] */
                FN_SCIF1_SCK, FN_PWM3, FN_TCLK2, FN_DU1_DG5,
-               FN_SSI_SDATA1_B, FN_CAN_TXCLK, FN_CC50_STATE34, 0,
+               FN_SSI_SDATA1_B, 0, 0, 0,
                /* IP9_27_25 [3] */
                FN_HSCIF1_HRTS_N, FN_SCIFA4_TXD, FN_IERX, FN_DU1_DG4,
-               FN_SSI_WS1_B, FN_CAN_STEP0, FN_CC50_STATE33, 0,
+               FN_SSI_WS1_B, 0, 0, 0,
                /* IP9_24_22 [3] */
                FN_HSCIF1_HCTS_N, FN_SCIFA4_RXD, FN_IECLK, FN_DU1_DG3,
-               FN_SSI_SCK1_B, FN_CAN_DEBUG_HW_TRIGGER, FN_CC50_STATE32, 0,
+               FN_SSI_SCK1_B, 0, 0, 0,
                /* IP9_21_19 [3] */
                FN_HSCIF1_HSCK, FN_PWM2, FN_IETX, FN_DU1_DG2,
-               FN_REMOCON_B, FN_SPEEDIN_B, FN_VSP_B, 0,
+               FN_REMOCON_B, FN_SPEEDIN_B, 0, 0,
                /* IP9_18_17 [2] */
                FN_HSCIF1_HTX, FN_I2C4_SDA, FN_TPUTO1, FN_DU1_DG1,
                /* IP9_16_15 [2] */
                FN_HSCIF1_HRX, FN_I2C4_SCL, FN_PWM6, FN_DU1_DG0,
                /* IP9_14_12 [3] */
                FN_MSIOF0_SS2, FN_SCIFA0_TXD, FN_TS_SPSYNC, FN_DU1_DR7,
-               FN_RIF1_D1, FN_FMIN_B, FN_RDS_DATA_B, 0,
+               0, FN_FMIN_B, 0, 0,
                /* IP9_11_9 [3] */
                FN_MSIOF0_SS1, FN_SCIFA0_RXD, FN_TS_SDEN, FN_DU1_DR6,
-               FN_RIF1_D0, FN_FMCLK_B, FN_RDS_CLK_B, 0,
+               0, FN_FMCLK_B, 0, 0,
                /* IP9_8_6 [3] */
                FN_MSIOF0_SYNC, FN_PWM1, FN_TS_SCK, FN_DU1_DR5,
-               FN_RIF1_CLK, FN_BPFCLK_B, 0, 0,
+               0, FN_BPFCLK_B, 0, 0,
                /* IP9_5_3 [3] */
                FN_MSIOF0_SCK, FN_IRQ0, FN_TS_SDATA, FN_DU1_DR4,
-               FN_RIF1_SYNC, FN_TPUTO1_C, 0, 0,
+               0, FN_TPUTO1_C, 0, 0,
                /* IP9_2_0 [3] */
                FN_MSIOF0_TXD, FN_SCIF5_TXD, FN_I2C2_SDA_C, FN_DU1_DR3,
-               FN_RIF1_D1_B, FN_TS_SPSYNC_D, FN_FMIN_C, FN_RDS_DATA, }
+               0, FN_TS_SPSYNC_D, FN_FMIN_C, 0, }
        },
        { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
                             2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
                /* IP10_31_30 [2] */
-               FN_SSI_SCK5, FN_SCIFA3_SCK, FN_DU1_DOTCLKIN, FN_CAN_DEBUGOUT10,
+               FN_SSI_SCK5, FN_SCIFA3_SCK, FN_DU1_DOTCLKIN, 0,
                /* IP10_29_27 [3] */
                FN_I2C2_SDA, FN_SCIFA5_TXD, FN_DU1_DB7, FN_AUDIO_CLKOUT_C,
-               FN_CAN_DEBUGOUT9, 0, 0, 0,
+               0, 0, 0, 0,
                /* IP10_26_24 [3] */
                FN_I2C2_SCL, FN_SCIFA5_RXD, FN_DU1_DB6, FN_AUDIO_CLKC_C,
-               FN_SSI_SDATA4_B, FN_CAN_DEBUGOUT8, 0, 0,
+               FN_SSI_SDATA4_B, 0, 0, 0,
                /* IP10_23_21 [3] */
                FN_SCIF3_TXD, FN_I2C1_SDA_E, FN_FMIN_D, FN_DU1_DB5,
-               FN_AUDIO_CLKB_C, FN_SSI_WS4_B, FN_CAN_DEBUGOUT7, FN_RDS_DATA_C,
+               FN_AUDIO_CLKB_C, FN_SSI_WS4_B, 0, 0,
                /* IP10_20_18 [3] */
                FN_SCIF3_RXD, FN_I2C1_SCL_E, FN_FMCLK_D, FN_DU1_DB4,
-               FN_AUDIO_CLKA_C, FN_SSI_SCK4_B, FN_CAN_DEBUGOUT6, FN_RDS_CLK_C,
+               FN_AUDIO_CLKA_C, FN_SSI_SCK4_B, 0, 0,
                /* IP10_17_15 [3] */
                FN_SCIF3_SCK, FN_IRQ2, FN_BPFCLK_D, FN_DU1_DB3,
-               FN_SSI_SDATA9_B, FN_TANS2, FN_CAN_DEBUGOUT5, FN_CC50_OSCOUT,
+               FN_SSI_SDATA9_B, 0, 0, 0,
                /* IP10_14_12 [3] */
                FN_SCIF2_SCK, FN_IRQ1, FN_DU1_DB2, FN_SSI_WS9_B,
-               FN_USB0_IDIN, FN_CAN_DEBUGOUT4, FN_CC50_STATE39, 0,
+               0, 0, 0, 0,
                /* IP10_11_9 [3] */
                FN_SCIF2_TXD, FN_IIC0_SDA, FN_DU1_DB1, FN_SSI_SCK9_B,
-               FN_USB0_OVC1, FN_CAN_DEBUGOUT3, FN_CC50_STATE38, 0,
+               0, 0, 0, 0,
                /* IP10_8_6 [3] */
                FN_SCIF2_RXD, FN_IIC0_SCL, FN_DU1_DB0, FN_SSI_SDATA2_B,
-               FN_USB0_EXTLP, FN_CAN_DEBUGOUT2, FN_CC50_STATE37, 0,
+               0, 0, 0, 0,
                /* IP10_5_3 [3] */
                FN_SCIF1_TXD, FN_I2C5_SDA, FN_DU1_DG7, FN_SSI_WS2_B,
-               FN_CAN_DEBUGOUT1, FN_CC50_STATE36, 0, 0,
+               0, 0, 0, 0,
                /* IP10_2_0 [3] */
                FN_SCIF1_RXD, FN_I2C5_SCL, FN_DU1_DG6, FN_SSI_SCK2_B,
-               FN_CAN_DEBUGOUT0, FN_CC50_STATE35, 0, 0, }
+               0, 0, 0, 0, }
        },
        { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
                             2, 3, 3, 3, 3, 2, 2, 3, 3, 2, 3, 3) {
@@ -4870,61 +4818,60 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                0, 0, 0, 0,
                /* IP11_29_27 [3] */
                FN_SSI_SDATA0, FN_MSIOF1_SCK_B, FN_PWM0_B, FN_ADICLK_B,
-               FN_AD_CLK_B, 0, 0, 0,
+               0, 0, 0, 0,
                /* IP11_26_24 [3] */
                FN_SSI_WS0129, FN_MSIOF1_TXD_B, FN_SCIF5_TXD_D, FN_ADICS_SAMP_B,
-               FN_AD_DO_B, 0, 0, 0,
+               0, 0, 0, 0,
                /* IP11_23_21 [3] */
                FN_SSI_SCK0129, FN_MSIOF1_RXD_B, FN_SCIF5_RXD_D, FN_ADIDATA_B,
-               FN_AD_DI_B, FN_PCMWE_N, 0, 0,
+               0, 0, 0, 0,
                /* IP11_20_18 [3] */
                FN_SSI_SDATA7, FN_SCIFA2_TXD_B, FN_IRQ8, FN_AUDIO_CLKA_D,
-               FN_CAN_CLK_D, FN_PCMOE_N, 0, 0,
+               FN_CAN_CLK_D, 0, 0, 0,
                /* IP11_17_16 [2] */
                FN_SSI_WS78, FN_SCIFA2_RXD_B, FN_I2C5_SCL_C, FN_DU1_CDE,
                /* IP11_15_14 [2] */
                FN_SSI_SCK78, FN_SCIFA2_SCK_B, FN_I2C5_SDA_C, FN_DU1_DISP,
                /* IP11_13_11 [3] */
                FN_SSI_SDATA6, FN_SCIFA1_TXD_B, FN_I2C4_SDA_C,
-               FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_CAN_DEBUGOUT15, 0, 0, 0,
+               FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, 0, 0, 0, 0,
                /* IP11_10_8 [3] */
                FN_SSI_WS6, FN_SCIFA1_RXD_B, FN_I2C4_SCL_C,
-               FN_DU1_EXVSYNC_DU1_VSYNC, FN_CAN_DEBUGOUT14, 0, 0, 0,
+               FN_DU1_EXVSYNC_DU1_VSYNC, 0, 0, 0, 0,
                /* IP11_7_6 [2] */
-               FN_SSI_SCK6, FN_SCIFA1_SCK_B, FN_DU1_EXHSYNC_DU1_HSYNC,
-               FN_CAN_DEBUGOUT13,
+               FN_SSI_SCK6, FN_SCIFA1_SCK_B, FN_DU1_EXHSYNC_DU1_HSYNC, 0,
                /* IP11_5_3 [3] */
                FN_SSI_SDATA5, FN_SCIFA3_TXD, FN_I2C3_SDA_C, FN_DU1_DOTCLKOUT1,
-               FN_CAN_DEBUGOUT12, 0, 0, 0,
+               0, 0, 0, 0,
                /* IP11_2_0 [3] */
                FN_SSI_WS5, FN_SCIFA3_RXD, FN_I2C3_SCL_C, FN_DU1_DOTCLKOUT0,
-               FN_CAN_DEBUGOUT11, 0, 0, 0, }
+               0, 0, 0, 0, }
        },
        { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
                             2, 3, 3, 3, 3, 3, 2, 2, 2, 3, 3, 3) {
                /* IP12_31_30 [2] */
                0, 0, 0, 0,
                /* IP12_29_27 [3] */
-               FN_SSI_SCK2, FN_HSCIF1_HTX_B, FN_VI1_DATA2, FN_MDATA,
+               FN_SSI_SCK2, FN_HSCIF1_HTX_B, FN_VI1_DATA2, 0,
                FN_ATAG0_N, FN_ETH_RXD1_B, 0, 0,
                /* IP12_26_24 [3] */
-               FN_SSI_SDATA1, FN_HSCIF1_HRX_B, FN_VI1_DATA1, FN_SDATA,
+               FN_SSI_SDATA1, FN_HSCIF1_HRX_B, FN_VI1_DATA1, 0,
                FN_ATAWR0_N, FN_ETH_RXD0_B, 0, 0,
                /* IP12_23_21 [3] */
                FN_SSI_WS1, FN_SCIF1_TXD_B, FN_IIC0_SDA_C, FN_VI1_DATA0,
-               FN_CAN0_TX_D, FN_AVB_AVTP_MATCH, FN_ETH_RX_ER_B, 0,
+               FN_CAN0_TX_D, 0, FN_ETH_RX_ER_B, 0,
                /* IP12_20_18 [3] */
                FN_SSI_SCK1, FN_SCIF1_RXD_B, FN_IIC0_SCL_C, FN_VI1_CLK,
-               FN_CAN0_RX_D, FN_AVB_AVTP_CAPTURE, FN_ETH_CRS_DV_B, 0,
+               FN_CAN0_RX_D, 0, FN_ETH_CRS_DV_B, 0,
                /* IP12_17_15 [3] */
                FN_SSI_SDATA8, FN_SCIF1_SCK_B, FN_PWM1_B, FN_IRQ9,
                FN_REMOCON, FN_DACK2, FN_ETH_MDIO_B, 0,
                /* IP12_14_13 [2] */
-               FN_SSI_SDATA4, FN_MLB_DAT, FN_IERX_B, FN_IRD_SCK,
+               FN_SSI_SDATA4, FN_MLB_DAT, FN_IERX_B, 0,
                /* IP12_12_11 [2] */
-               FN_SSI_WS4, FN_MLB_SIG, FN_IECLK_B, FN_IRD_RX,
+               FN_SSI_WS4, FN_MLB_SIG, FN_IECLK_B, 0,
                /* IP12_10_9 [2] */
-               FN_SSI_SCK4, FN_MLB_CLK, FN_IETX_B, FN_IRD_TX,
+               FN_SSI_SCK4, FN_MLB_CLK, FN_IETX_B, 0,
                /* IP12_8_6 [3] */
                FN_SSI_SDATA3, FN_MSIOF1_SS2_B, FN_SCIFA1_TXD_C, FN_ADICHS2_B,
                FN_CAN1_TX_C, FN_DREQ2_N, 0, 0,
@@ -4933,7 +4880,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                FN_CAN1_RX_C, FN_DACK1_B, 0, 0,
                /* IP12_2_0 [3] */
                FN_SSI_SCK34, FN_MSIOF1_SYNC_B, FN_SCIFA1_SCK_C, FN_ADICHS0_B,
-               FN_AD_NCS_N_B, FN_DREQ1_N_B, 0, 0, }
+               0, FN_DREQ1_N_B, 0, 0, }
        },
        { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
                             1, 1, 1, 1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
@@ -4949,16 +4896,16 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                0, 0,
                /* IP13_26_24 [3] */
                FN_AUDIO_CLKOUT, FN_I2C4_SDA_B, FN_SCIFA5_TXD_D, FN_VI1_VSYNC_N,
-               FN_TS_SPSYNC_C, FN_RIF0_D1_B, FN_FMIN_E, FN_RDS_DATA_D,
+               FN_TS_SPSYNC_C, 0, FN_FMIN_E, 0,
                /* IP13_23_21 [3] */
                FN_AUDIO_CLKC, FN_I2C4_SCL_B, FN_SCIFA5_RXD_D, FN_VI1_HSYNC_N,
-               FN_TS_SDEN_C, FN_RIF0_D0_B, FN_FMCLK_E, FN_RDS_CLK_D,
+               FN_TS_SDEN_C, 0, FN_FMCLK_E, 0,
                /* IP13_20_18 [3] */
                FN_AUDIO_CLKB, FN_I2C0_SDA_B, FN_SCIFA4_TXD_D, FN_VI1_FIELD,
-               FN_TS_SCK_C, FN_RIF0_CLK_B, FN_BPFCLK_E, FN_ETH_MDC_B,
+               FN_TS_SCK_C, 0, FN_BPFCLK_E, FN_ETH_MDC_B,
                /* IP13_17_15 [3] */
                FN_AUDIO_CLKA, FN_I2C0_SCL_B, FN_SCIFA4_RXD_D, FN_VI1_CLKENB,
-               FN_TS_SDATA_C, FN_RIF0_SYNC_B, FN_ETH_TXD0_B, 0,
+               FN_TS_SDATA_C, 0, FN_ETH_TXD0_B, 0,
                /* IP13_14_12 [3] */
                FN_SSI_SDATA9, FN_SCIF2_TXD_B, FN_I2C3_SDA_E, FN_VI1_DATA7,
                FN_ATADIR0_N, FN_ETH_MAGIC_B, 0, 0,
@@ -4967,38 +4914,32 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                FN_ATARD0_N, FN_ETH_TX_EN_B, 0, 0,
                /* IP13_8_6 [3] */
                FN_SSI_SCK9, FN_SCIF2_SCK_B, FN_PWM2_B, FN_VI1_DATA5,
-               FN_MTS_N, FN_EX_WAIT1, FN_ETH_TXD1_B, 0,
+               0, FN_EX_WAIT1, FN_ETH_TXD1_B, 0,
                /* IP13_5_3 [2] */
                FN_SSI_SDATA2, FN_HSCIF1_HRTS_N_B, FN_SCIFA0_TXD_D,
-               FN_VI1_DATA4, FN_STM_N, FN_ATACS10_N, FN_ETH_REFCLK_B, 0,
+               FN_VI1_DATA4, 0, FN_ATACS10_N, FN_ETH_REFCLK_B, 0,
                /* IP13_2_0 [3] */
                FN_SSI_WS2, FN_HSCIF1_HCTS_N_B, FN_SCIFA0_RXD_D, FN_VI1_DATA3,
-               FN_SCKZ, FN_ATACS00_N, FN_ETH_LINK_B, 0, }
+               0, FN_ATACS00_N, FN_ETH_LINK_B, 0, }
        },
        { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
-                            2, 1, 2, 3, 1, 1, 1, 1, 1, 1, 3, 3, 3, 3, 3,
+                            2, 1, 2, 3, 4, 1, 1, 3, 3, 3, 3, 3,
                             2, 1) {
                /* SEL_ADG [2] */
                FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3,
-               /* SEL_ADI [1] */
-               FN_SEL_ADI_0, FN_SEL_ADI_1,
+               /* RESERVED [1] */
+               0, 0,
                /* SEL_CAN [2] */
                FN_SEL_CAN_0, FN_SEL_CAN_1, FN_SEL_CAN_2, FN_SEL_CAN_3,
                /* SEL_DARC [3] */
                FN_SEL_DARC_0, FN_SEL_DARC_1, FN_SEL_DARC_2, FN_SEL_DARC_3,
                FN_SEL_DARC_4, 0, 0, 0,
-               /* SEL_DR0 [1] */
-               FN_SEL_DR0_0, FN_SEL_DR0_1,
-               /* SEL_DR1 [1] */
-               FN_SEL_DR1_0, FN_SEL_DR1_1,
-               /* SEL_DR2 [1] */
-               FN_SEL_DR2_0, FN_SEL_DR2_1,
-               /* SEL_DR3 [1] */
-               FN_SEL_DR3_0, FN_SEL_DR3_1,
+               /* RESERVED [4] */
+               0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
                /* SEL_ETH [1] */
                FN_SEL_ETH_0, FN_SEL_ETH_1,
-               /* SLE_FSN [1] */
-               FN_SEL_FSN_0, FN_SEL_FSN_1,
+               /* RESERVED [1] */
+               0, 0,
                /* SEL_IC200 [3] */
                FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, FN_SEL_I2C00_3,
                FN_SEL_I2C00_4, 0, 0, 0,
@@ -5016,8 +4957,8 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                FN_SEL_I2C04_4, 0, 0, 0,
                /* SEL_I2C05 [2] */
                FN_SEL_I2C05_0, FN_SEL_I2C05_1, FN_SEL_I2C05_2, FN_SEL_I2C05_3,
-               /* SEL_AVB [1] */
-               FN_SEL_AVB_0, FN_SEL_AVB_1, }
+               /* RESERVED [1] */
+               0, 0, }
        },
        { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
                             2, 2, 1, 1, 1, 1, 1, 1, 2, 2, 1, 1, 2, 2, 1, 1,
@@ -5053,8 +4994,8 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                /* SEL_SCIFA5 [2] */
                FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2,
                FN_SEL_SCIFA5_3,
-               /* SEL_SPDM [1] */
-               FN_SEL_SPDM_0, FN_SEL_SPDM_1,
+               /* RESERVED [1] */
+               0, 0,
                /* SEL_TMU [1] */
                FN_SEL_TMU_0, FN_SEL_TMU_1,
                /* SEL_TSIF0 [2] */
@@ -5067,8 +5008,8 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1,
                /* SEL_HSCIF1 [1] */
                FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
-               /* SEL_RDS [2] */
-               FN_SEL_RDS_0, FN_SEL_RDS_1, FN_SEL_RDS_2, FN_SEL_RDS_3, }
+               /* RESERVED [2] */
+               0, 0, 0, 0, }
        },
        { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
                             2, 2, 2, 1, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1,