drm/i915: pass dev_priv explicitly to PIPE_DATA_N1

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PIPE_DATA_N1 register macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/80759c6efdfdb59c4bd624af85b9db38ebe06f65.1717514638.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 7fd65e3b018d79b925b40b61613eebc324e722c4..5eb4ad261c215ca27cb3c488ba47317bd5be3914 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2642,7 +2642,7 @@ void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc,
        if (DISPLAY_VER(dev_priv) >= 5)
                intel_set_m_n(dev_priv, m_n,
                              PIPE_DATA_M1(dev_priv, transcoder),
-                             PIPE_DATA_N1(transcoder),
+                             PIPE_DATA_N1(dev_priv, transcoder),
                              PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder));
        else
                intel_set_m_n(dev_priv, m_n,
@@ -3339,7 +3339,7 @@ void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc,
        if (DISPLAY_VER(dev_priv) >= 5)
                intel_get_m_n(dev_priv, m_n,
                              PIPE_DATA_M1(dev_priv, transcoder),
-                             PIPE_DATA_N1(transcoder),
+                             PIPE_DATA_N1(dev_priv, transcoder),
                              PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder));
        else
                intel_get_m_n(dev_priv, m_n,

diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c
index ce6f20b1dabcb79649e0279d3201508d0288c0b8..5f3ee57b59823723b196985005b108a0242d0900 100644 (file)
--- a/drivers/gpu/drm/i915/gvt/display.c
+++ b/drivers/gpu/drm/i915/gvt/display.c
@@ -263,7 +263,7 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
                 */
                vgpu_vreg_t(vgpu, PIPE_DATA_M1(dev_priv, TRANSCODER_A)) = TU_SIZE(64);
                vgpu_vreg_t(vgpu, PIPE_DATA_M1(dev_priv, TRANSCODER_A)) |= 0x5b425e;
-               vgpu_vreg_t(vgpu, PIPE_DATA_N1(TRANSCODER_A)) = 0x800000;
+               vgpu_vreg_t(vgpu, PIPE_DATA_N1(dev_priv, TRANSCODER_A)) = 0x800000;
                vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A)) = 0x3cd6e;
                vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)) = 0x80000;
 
@@ -397,7 +397,7 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
                 */
                vgpu_vreg_t(vgpu, PIPE_DATA_M1(dev_priv, TRANSCODER_A)) = TU_SIZE(64);
                vgpu_vreg_t(vgpu, PIPE_DATA_M1(dev_priv, TRANSCODER_A)) |= 0x5b425e;
-               vgpu_vreg_t(vgpu, PIPE_DATA_N1(TRANSCODER_A)) = 0x800000;
+               vgpu_vreg_t(vgpu, PIPE_DATA_N1(dev_priv, TRANSCODER_A)) = 0x800000;
                vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A)) = 0x3cd6e;
                vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)) = 0x80000;
        }

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e7b7f8ac8ae2804d5f44ba4a71a2ed7b1744e0b0..762b2e43051cea23868341762f0a3154a82ae90a 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2299,7 +2299,7 @@
 #define _PIPEB_LINK_N2         0x6104c
 
 #define PIPE_DATA_M1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_M1)
-#define PIPE_DATA_N1(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_N1)
+#define PIPE_DATA_N1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_N1)
 #define PIPE_DATA_M2(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_M2)
 #define PIPE_DATA_N2(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_N2)
 #define PIPE_LINK_M1(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_M1)

diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index 977d695fbdff4ce98c076feede56d016828ff501..b9ad4eec474040bfd9ca3251b9913241a6b79c6b 100644 (file)
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -267,7 +267,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
        MMIO_D(BCLRPAT(dev_priv, TRANSCODER_EDP));
        MMIO_D(TRANS_VSYNCSHIFT(dev_priv, TRANSCODER_EDP));
        MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_A));
-       MMIO_D(PIPE_DATA_N1(TRANSCODER_A));
+       MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_A));
        MMIO_D(PIPE_DATA_M2(TRANSCODER_A));
        MMIO_D(PIPE_DATA_N2(TRANSCODER_A));
        MMIO_D(PIPE_LINK_M1(TRANSCODER_A));
@@ -275,7 +275,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
        MMIO_D(PIPE_LINK_M2(TRANSCODER_A));
        MMIO_D(PIPE_LINK_N2(TRANSCODER_A));
        MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_B));
-       MMIO_D(PIPE_DATA_N1(TRANSCODER_B));
+       MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_B));
        MMIO_D(PIPE_DATA_M2(TRANSCODER_B));
        MMIO_D(PIPE_DATA_N2(TRANSCODER_B));
        MMIO_D(PIPE_LINK_M1(TRANSCODER_B));
@@ -283,7 +283,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
        MMIO_D(PIPE_LINK_M2(TRANSCODER_B));
        MMIO_D(PIPE_LINK_N2(TRANSCODER_B));
        MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_C));
-       MMIO_D(PIPE_DATA_N1(TRANSCODER_C));
+       MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_C));
        MMIO_D(PIPE_DATA_M2(TRANSCODER_C));
        MMIO_D(PIPE_DATA_N2(TRANSCODER_C));
        MMIO_D(PIPE_LINK_M1(TRANSCODER_C));
@@ -291,7 +291,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
        MMIO_D(PIPE_LINK_M2(TRANSCODER_C));
        MMIO_D(PIPE_LINK_N2(TRANSCODER_C));
        MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_EDP));
-       MMIO_D(PIPE_DATA_N1(TRANSCODER_EDP));
+       MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_EDP));
        MMIO_D(PIPE_DATA_M2(TRANSCODER_EDP));
        MMIO_D(PIPE_DATA_N2(TRANSCODER_EDP));
        MMIO_D(PIPE_LINK_M1(TRANSCODER_EDP));