arm64/sysreg: Convert ID_PFR1_EL1 to automatic generation

Convert ID_PFR1_EL1 to be automatically generated as per DDI0487I.a,
no functional changes.

Reviewed-by: Mark Brown <broonie@kernel.org>
Signed-off-by: James Morse <james.morse@arm.com>
Link: https://lore.kernel.org/r/20221130171637.718182-31-james.morse@arm.com
Signed-off-by: Will Deacon <will@kernel.org>

diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 72b32e179b46dd3a5db983096df3fe2a0e086589..85197dd180e09a9e489a63bfb19023ee76fc5349 100644 (file)
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -165,7 +165,6 @@
 #define SYS_MPIDR_EL1                  sys_reg(3, 0, 0, 0, 5)
 #define SYS_REVIDR_EL1                 sys_reg(3, 0, 0, 0, 6)
 
-#define SYS_ID_PFR1_EL1                        sys_reg(3, 0, 0, 1, 1)
 #define SYS_ID_PFR2_EL1                        sys_reg(3, 0, 0, 3, 4)
 #define SYS_ID_DFR0_EL1                        sys_reg(3, 0, 0, 1, 2)
 #define SYS_ID_DFR1_EL1                        sys_reg(3, 0, 0, 3, 5)
@@ -716,15 +715,6 @@
 #define MVFR1_EL1_FPDNaN_SHIFT 4
 #define MVFR1_EL1_FPFtZ_SHIFT  0
 
-#define ID_PFR1_EL1_GIC_SHIFT          28
-#define ID_PFR1_EL1_Virt_frac_SHIFT    24
-#define ID_PFR1_EL1_Sec_frac_SHIFT     20
-#define ID_PFR1_EL1_GenTimer_SHIFT     16
-#define ID_PFR1_EL1_Virtualization_SHIFT 12
-#define ID_PFR1_EL1_MProgMod_SHIFT     8
-#define ID_PFR1_EL1_Security_SHIFT     4
-#define ID_PFR1_EL1_ProgMod_SHIFT      0
-
 #if defined(CONFIG_ARM64_4K_PAGES)
 #define ID_AA64MMFR0_EL1_TGRAN_SHIFT           ID_AA64MMFR0_EL1_TGRAN4_SHIFT
 #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN   ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MIN

diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index 641bd7e3365c4f5dc2c9813c2828ffcd06153c5e..e86193b295e4285d7cf4288460b4d9561f33c5c4 100644 (file)
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -87,6 +87,46 @@ Enum 3:0     State0
 EndEnum
 EndSysreg
 
+Sysreg ID_PFR1_EL1     3       0       0       1       1
+Res0   63:32
+Enum   31:28   GIC
+       0b0000  NI
+       0b0001  GICv3
+       0b0010  GICv4p1
+EndEnum
+Enum   27:24   Virt_frac
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+Enum   23:20   Sec_frac
+       0b0000  NI
+       0b0001  WALK_DISABLE
+       0b0010  SECURE_MEMORY
+EndEnum
+Enum   19:16   GenTimer
+       0b0000  NI
+       0b0001  IMP
+       0b0010  ECV
+EndEnum
+Enum   15:12   Virtualization
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+Enum   11:8    MProgMod
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+Enum   7:4     Security
+       0b0000  NI
+       0b0001  EL3
+       0b0001  NSACR_RFR
+EndEnum
+Enum   3:0     ProgMod
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+EndSysreg
+
 Sysreg ID_MMFR0_EL1    3       0       0       1       4
 Res0   63:32
 Enum   31:28   InnerShr