clk: renesas: rcar-gen4: Restore PLL enum sort order
authorGeert Uytterhoeven <geert+renesas@glider.be>
Tue, 29 Nov 2022 16:54:58 +0000 (17:54 +0100)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Mon, 26 Dec 2022 10:00:05 +0000 (11:00 +0100)
When CLK_TYPE_GEN4_PLL4 was added to the rcar_gen4_clk_types enum, it
was inserted at a random location.  Restore sort order of the clock
types referring to PLLs.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/dbd61ed19f79e9ae751fbb533d6c946e810e4359.1669740824.git.geert+renesas@glider.be
drivers/clk/renesas/rcar-gen4-cpg.h

index 0b15dcfdca7b5af7c973476704c4f8d0f7841c4a..0a0e3bdb3a664c103a5a39c52078410c580a5d54 100644 (file)
@@ -15,8 +15,8 @@ enum rcar_gen4_clk_types {
        CLK_TYPE_GEN4_PLL2,
        CLK_TYPE_GEN4_PLL2X_3X, /* r8a779a0 only */
        CLK_TYPE_GEN4_PLL3,
-       CLK_TYPE_GEN4_PLL5,
        CLK_TYPE_GEN4_PLL4,
+       CLK_TYPE_GEN4_PLL5,
        CLK_TYPE_GEN4_PLL6,
        CLK_TYPE_GEN4_SDSRC,
        CLK_TYPE_GEN4_SDH,