drm/xe: Add missing DG2 lrc tunings

Synchronize with i915 the DG2 tunings as of
commit 4d14d7717f19 ("drm/i915/selftest: Fix ktime_get() and h/w access
order").

Contrary to the tuning "gang timer" for TGL, there is no quick
justification for why the read back is disabled in i915. Keep it
with that flag for now. That can be tentatively removed later when the
read values are checked.

v2: Use XEHP_FF_MODE2 instead of GEN12_FF_MODE2 (Matt Roper)

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://lore.kernel.org/r/20230314003012.2600353-11-lucas.demarchi@intel.com
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
index 9320cb01d4240065a85bbb7d705091438fcd6ce5..97a9d78e883144dcf77c2bbf0f77973034fa29cf 100644 (file)
--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -73,7 +73,11 @@
 #define XEHP_TILE0_ADDR_RANGE                  MCR_REG(0x4900)
 #define XEHP_FLAT_CCS_BASE_ADDR                        MCR_REG(0x4910)
 
+#define CHICKEN_RASTER_2                       MCR_REG(0x6208)
+#define   TBIMR_FAST_CLIP                      REG_BIT(5)
+
 #define GEN12_FF_MODE2                         _MMIO(0x6604)
+#define XEHP_FF_MODE2                          MCR_REG(0x6604)
 #define   FF_MODE2_GS_TIMER_MASK               REG_GENMASK(31, 24)
 #define   FF_MODE2_GS_TIMER_224                        REG_FIELD_PREP(FF_MODE2_GS_TIMER_MASK, 224)
 #define   FF_MODE2_TDS_TIMER_MASK              REG_GENMASK(23, 16)
@@ -228,6 +232,9 @@
 #define XEHP_L3NODEARBCFG                      MCR_REG(0xb0b4)
 #define   XEHP_LNESPARE                                REG_BIT(19)
 
+#define XEHP_L3SQCREG5                         MCR_REG(0xb158)
+#define   L3_PWM_TIMER_INIT_VAL_MASK           REG_GENMASK(9, 0)
+
 #define XEHP_L3SCQREG7                         MCR_REG(0xb188)
 #define   BLEND_FILL_CACHING_OPT_DIS           REG_BIT(3)
 

diff --git a/drivers/gpu/drm/xe/xe_tuning.c b/drivers/gpu/drm/xe/xe_tuning.c
index 47b27dccb38542f87e8d044f243650af20d972f4..7ff5eb762da547f148360ac2136e12ed86653cbc 100644 (file)
--- a/drivers/gpu/drm/xe/xe_tuning.c
+++ b/drivers/gpu/drm/xe/xe_tuning.c
@@ -35,6 +35,26 @@ static const struct xe_rtp_entry lrc_tunings[] = {
                                                FF_MODE2_GS_TIMER_MASK,
                                                FF_MODE2_GS_TIMER_224))
        },
+
+       /* DG2 */
+
+       { XE_RTP_NAME("Tuning: L3 cache"),
+         XE_RTP_RULES(PLATFORM(DG2)),
+         XE_RTP_ACTIONS(FIELD_SET(XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,
+                                  REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f)))
+       },
+       { XE_RTP_NAME("Tuning: TDS gang timer"),
+         XE_RTP_RULES(PLATFORM(DG2)),
+         /* read verification is ignored as in i915 - need to check enabling */
+         XE_RTP_ACTIONS(FIELD_SET_NO_READ_MASK(XEHP_FF_MODE2,
+                                               FF_MODE2_TDS_TIMER_MASK,
+                                               FF_MODE2_TDS_TIMER_128))
+       },
+       { XE_RTP_NAME("Tuning: TBIMR fast clip"),
+         XE_RTP_RULES(PLATFORM(DG2)),
+         XE_RTP_ACTIONS(SET(CHICKEN_RASTER_2, TBIMR_FAST_CLIP,
+                            XE_RTP_ACTION_FLAG(MASKED_REG)))
+       },
        {}
 };