drm/i915: pass dev_priv explicitly to CURSURFLIVE

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the CURSURFLIVE register macro.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/86aa98ad9f883681f5c2e3aba839d02d8591bfbf.1715774156.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/display/intel_cursor_regs.h b/drivers/gpu/drm/i915/display/intel_cursor_regs.h
index 3e948526e9abe16c72e244f82f8e6b0f8bb7f1c9..c2190af1e9f57d0491bc315f990b5f894a5c9751 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_cursor_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cursor_regs.h
@@ -73,7 +73,7 @@
 #define CURSIZE(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURASIZE)
 #define CUR_FBC_CTL(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CUR_FBC_CTL_A)
 #define CUR_CHICKEN(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CUR_CHICKEN_A)
-#define CURSURFLIVE(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURASURFLIVE)
+#define CURSURFLIVE(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURASURFLIVE)
 
 /* skl+ */
 #define _CUR_WM_A_0            0x70140

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 98dfd537070c0b1228912c8aa1dd5f3d0b252a5f..df0d14a5023f389ec75caadd1c94737a25170a4a 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -2352,7 +2352,7 @@ static void psr_force_hw_tracking_exit(struct intel_dp *intel_dp)
         * but testing proved that it works for up display 13, for newer
         * than that testing will be needed.
         */
-       intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0);
+       intel_de_write(dev_priv, CURSURFLIVE(dev_priv, intel_dp->psr.pipe), 0);
 }
 
 void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_state)
@@ -3100,7 +3100,9 @@ static void _psr_invalidate_handle(struct intel_dp *intel_dp)
 
                if (intel_dp->psr.psr2_sel_fetch_cff_enabled) {
                        /* Send one update otherwise lag is observed in screen */
-                       intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0);
+                       intel_de_write(dev_priv,
+                                      CURSURFLIVE(dev_priv, intel_dp->psr.pipe),
+                                      0);
                        return;
                }
 
@@ -3110,7 +3112,8 @@ static void _psr_invalidate_handle(struct intel_dp *intel_dp)
                intel_de_write(dev_priv,
                               PSR2_MAN_TRK_CTL(dev_priv, cpu_transcoder),
                               val);
-               intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0);
+               intel_de_write(dev_priv,
+                              CURSURFLIVE(dev_priv, intel_dp->psr.pipe), 0);
                intel_dp->psr.psr2_sel_fetch_cff_enabled = true;
        } else {
                intel_psr_exit(intel_dp);
@@ -3210,7 +3213,9 @@ static void _psr_flush_handle(struct intel_dp *intel_dp)
                                intel_de_write(dev_priv,
                                               PSR2_MAN_TRK_CTL(dev_priv, cpu_transcoder),
                                               val);
-                               intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0);
+                               intel_de_write(dev_priv,
+                                              CURSURFLIVE(dev_priv, intel_dp->psr.pipe),
+                                              0);
                                intel_dp->psr.psr2_sel_fetch_cff_enabled = false;
                        }
                } else {