drm/i915: refactor PCH_DPLL_SEL #defines
authorDaniel Vetter <daniel.vetter@ffwll.ch>
Wed, 5 Jun 2013 11:34:09 +0000 (13:34 +0200)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Mon, 10 Jun 2013 17:48:56 +0000 (19:48 +0200)
The bits are evenly space, so we can cut down on two big switch
blocks. This also greatly simplifies the hw state readout which
follows in the next patch.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_reg.h
drivers/gpu/drm/i915/intel_display.c

index b1fdca9e96bbf85946e828a794f2769c55971401..99638fc6285bec3e9a13d2bcd8147f538054e630 100644 (file)
 #define PCH_SSC4_AUX_PARMS      0xc6214
 
 #define PCH_DPLL_SEL           0xc7000
-#define  TRANSA_DPLL_ENABLE    (1<<3)
-#define         TRANSA_DPLLB_SEL       (1<<0)
-#define         TRANSA_DPLLA_SEL       0
-#define  TRANSB_DPLL_ENABLE    (1<<7)
-#define         TRANSB_DPLLB_SEL       (1<<4)
-#define         TRANSB_DPLLA_SEL       (0)
-#define  TRANSC_DPLL_ENABLE    (1<<11)
-#define         TRANSC_DPLLB_SEL       (1<<8)
-#define         TRANSC_DPLLA_SEL       (0)
+#define         TRANS_DPLLB_SEL(pipe)          (1 << (pipe * 4))
+#define         TRANS_DPLLA_SEL(pipe)          0
+#define  TRANS_DPLL_ENABLE(pipe)       (1 << (pipe * 4 + 3))
 
 /* transcoder */
 
index a5ccce07386b2bf7e8c96d278b96a59bc306c728..d5932ef76cde4a785d49152ca903b5a8eed2e642 100644 (file)
@@ -2986,21 +2986,8 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
                u32 sel;
 
                temp = I915_READ(PCH_DPLL_SEL);
-               switch (pipe) {
-               default:
-               case 0:
-                       temp |= TRANSA_DPLL_ENABLE;
-                       sel = TRANSA_DPLLB_SEL;
-                       break;
-               case 1:
-                       temp |= TRANSB_DPLL_ENABLE;
-                       sel = TRANSB_DPLLB_SEL;
-                       break;
-               case 2:
-                       temp |= TRANSC_DPLL_ENABLE;
-                       sel = TRANSC_DPLLB_SEL;
-                       break;
-               }
+               temp |= TRANS_DPLL_ENABLE(pipe);
+               sel = TRANS_DPLLB_SEL(pipe);
                if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
                        temp |= sel;
                else
@@ -3480,20 +3467,7 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
 
                        /* disable DPLL_SEL */
                        temp = I915_READ(PCH_DPLL_SEL);
-                       switch (pipe) {
-                       case 0:
-                               temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
-                               break;
-                       case 1:
-                               temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
-                               break;
-                       case 2:
-                               /* C shares PLL A or B */
-                               temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
-                               break;
-                       default:
-                               BUG(); /* wtf */
-                       }
+                       temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
                        I915_WRITE(PCH_DPLL_SEL, temp);
                }