drm/i915/ddi: split up intel_ddi_read_func_ctl() by output type

The function has become quite long, and the switch-case statement quite
complex with the fallthrougs. Simplify by splitting to individual
functions and an if-ladder.

This highlights how TRANS_DDI_MODE_SELECT_FDI_OR_128B132B works on
different platforms.

Reviewed-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/2621df6e6b0b7ac75159cfb112755c35b30ce906.1732106557.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index f8edb604d462a328edd7231da5d0723e47438cdc..607c983f07efb461d6ff0d04d0baa6ce4d4af34d 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3908,15 +3908,122 @@ static void bdw_get_trans_port_sync_config(struct intel_crtc_state *crtc_state)
                    crtc_state->sync_mode_slaves_mask);
 }
 
+static void intel_ddi_read_func_ctl_dvi(struct intel_encoder *encoder,
+                                       struct intel_crtc_state *crtc_state,
+                                       u32 ddi_func_ctl)
+{
+       struct intel_display *display = to_intel_display(encoder);
+
+       crtc_state->output_types |= BIT(INTEL_OUTPUT_HDMI);
+       if (DISPLAY_VER(display) >= 14)
+               crtc_state->lane_count =
+                       ((ddi_func_ctl & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
+       else
+               crtc_state->lane_count = 4;
+}
+
+static void intel_ddi_read_func_ctl_hdmi(struct intel_encoder *encoder,
+                                        struct intel_crtc_state *crtc_state,
+                                        u32 ddi_func_ctl)
+{
+       crtc_state->has_hdmi_sink = true;
+
+       crtc_state->infoframes.enable |=
+               intel_hdmi_infoframes_enabled(encoder, crtc_state);
+
+       if (crtc_state->infoframes.enable)
+               crtc_state->has_infoframe = true;
+
+       if (ddi_func_ctl & TRANS_DDI_HDMI_SCRAMBLING)
+               crtc_state->hdmi_scrambling = true;
+       if (ddi_func_ctl & TRANS_DDI_HIGH_TMDS_CHAR_RATE)
+               crtc_state->hdmi_high_tmds_clock_ratio = true;
+
+       intel_ddi_read_func_ctl_dvi(encoder, crtc_state, ddi_func_ctl);
+}
+
+static void intel_ddi_read_func_ctl_fdi(struct intel_encoder *encoder,
+                                       struct intel_crtc_state *crtc_state,
+                                       u32 ddi_func_ctl)
+{
+       struct intel_display *display = to_intel_display(encoder);
+
+       crtc_state->output_types |= BIT(INTEL_OUTPUT_ANALOG);
+       crtc_state->enhanced_framing =
+               intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)) &
+               DP_TP_CTL_ENHANCED_FRAME_ENABLE;
+}
+
+static void intel_ddi_read_func_ctl_dp_sst(struct intel_encoder *encoder,
+                                          struct intel_crtc_state *crtc_state,
+                                          u32 ddi_func_ctl)
+{
+       struct intel_display *display = to_intel_display(encoder);
+       struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+       struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
+       enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+
+       if (encoder->type == INTEL_OUTPUT_EDP)
+               crtc_state->output_types |= BIT(INTEL_OUTPUT_EDP);
+       else
+               crtc_state->output_types |= BIT(INTEL_OUTPUT_DP);
+       crtc_state->lane_count =
+               ((ddi_func_ctl & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
+
+       intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, &crtc_state->dp_m_n);
+       intel_cpu_transcoder_get_m2_n2(crtc, cpu_transcoder, &crtc_state->dp_m2_n2);
+
+       crtc_state->enhanced_framing =
+               intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)) &
+               DP_TP_CTL_ENHANCED_FRAME_ENABLE;
+
+       if (DISPLAY_VER(display) >= 11)
+               crtc_state->fec_enable =
+                       intel_de_read(display,
+                                     dp_tp_ctl_reg(encoder, crtc_state)) & DP_TP_CTL_FEC_ENABLE;
+
+       if (dig_port->lspcon.active && intel_dp_has_hdmi_sink(&dig_port->dp))
+               crtc_state->infoframes.enable |=
+                       intel_lspcon_infoframes_enabled(encoder, crtc_state);
+       else
+               crtc_state->infoframes.enable |=
+                       intel_hdmi_infoframes_enabled(encoder, crtc_state);
+}
+
+static void intel_ddi_read_func_ctl_dp_mst(struct intel_encoder *encoder,
+                                          struct intel_crtc_state *crtc_state,
+                                          u32 ddi_func_ctl)
+{
+       struct intel_display *display = to_intel_display(encoder);
+       struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+       enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+
+       crtc_state->output_types |= BIT(INTEL_OUTPUT_DP_MST);
+       crtc_state->lane_count =
+               ((ddi_func_ctl & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
+
+       if (DISPLAY_VER(display) >= 12)
+               crtc_state->mst_master_transcoder =
+                       REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, ddi_func_ctl);
+
+       intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, &crtc_state->dp_m_n);
+
+       if (DISPLAY_VER(display) >= 11)
+               crtc_state->fec_enable =
+                       intel_de_read(display,
+                                     dp_tp_ctl_reg(encoder, crtc_state)) & DP_TP_CTL_FEC_ENABLE;
+
+       crtc_state->infoframes.enable |=
+               intel_hdmi_infoframes_enabled(encoder, crtc_state);
+}
+
 static void intel_ddi_read_func_ctl(struct intel_encoder *encoder,
                                    struct intel_crtc_state *pipe_config)
 {
        struct intel_display *display = to_intel_display(encoder);
        struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-       struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
        enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
-       struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
-       u32 ddi_func_ctl, flags = 0;
+       u32 ddi_func_ctl, ddi_mode, flags = 0;
 
        ddi_func_ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder));
        if (ddi_func_ctl & TRANS_DDI_PHSYNC)
@@ -3947,90 +4054,19 @@ static void intel_ddi_read_func_ctl(struct intel_encoder *encoder,
                break;
        }
 
-       switch (ddi_func_ctl & TRANS_DDI_MODE_SELECT_MASK) {
-       case TRANS_DDI_MODE_SELECT_HDMI:
-               pipe_config->has_hdmi_sink = true;
-
-               pipe_config->infoframes.enable |=
-                       intel_hdmi_infoframes_enabled(encoder, pipe_config);
-
-               if (pipe_config->infoframes.enable)
-                       pipe_config->has_infoframe = true;
-
-               if (ddi_func_ctl & TRANS_DDI_HDMI_SCRAMBLING)
-                       pipe_config->hdmi_scrambling = true;
-               if (ddi_func_ctl & TRANS_DDI_HIGH_TMDS_CHAR_RATE)
-                       pipe_config->hdmi_high_tmds_clock_ratio = true;
-               fallthrough;
-       case TRANS_DDI_MODE_SELECT_DVI:
-               pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
-               if (DISPLAY_VER(dev_priv) >= 14)
-                       pipe_config->lane_count =
-                               ((ddi_func_ctl & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
-               else
-                       pipe_config->lane_count = 4;
-               break;
-       case TRANS_DDI_MODE_SELECT_DP_SST:
-               if (encoder->type == INTEL_OUTPUT_EDP)
-                       pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
-               else
-                       pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
-               pipe_config->lane_count =
-                       ((ddi_func_ctl & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
-
-               intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder,
-                                              &pipe_config->dp_m_n);
-               intel_cpu_transcoder_get_m2_n2(crtc, cpu_transcoder,
-                                              &pipe_config->dp_m2_n2);
-
-               pipe_config->enhanced_framing =
-                       intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, pipe_config)) &
-                       DP_TP_CTL_ENHANCED_FRAME_ENABLE;
-
-               if (DISPLAY_VER(dev_priv) >= 11)
-                       pipe_config->fec_enable =
-                               intel_de_read(dev_priv,
-                                             dp_tp_ctl_reg(encoder, pipe_config)) & DP_TP_CTL_FEC_ENABLE;
-
-               if (dig_port->lspcon.active && intel_dp_has_hdmi_sink(&dig_port->dp))
-                       pipe_config->infoframes.enable |=
-                               intel_lspcon_infoframes_enabled(encoder, pipe_config);
-               else
-                       pipe_config->infoframes.enable |=
-                               intel_hdmi_infoframes_enabled(encoder, pipe_config);
-               break;
-       case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B:
-               if (!HAS_DP20(display)) {
-                       /* FDI */
-                       pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
-                       pipe_config->enhanced_framing =
-                               intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, pipe_config)) &
-                               DP_TP_CTL_ENHANCED_FRAME_ENABLE;
-                       break;
-               }
-               fallthrough; /* 128b/132b */
-       case TRANS_DDI_MODE_SELECT_DP_MST:
-               pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST);
-               pipe_config->lane_count =
-                       ((ddi_func_ctl & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
-
-               if (DISPLAY_VER(dev_priv) >= 12)
-                       pipe_config->mst_master_transcoder =
-                               REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, ddi_func_ctl);
-
-               intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder,
-                                              &pipe_config->dp_m_n);
-
-               if (DISPLAY_VER(dev_priv) >= 11)
-                       pipe_config->fec_enable =
-                               intel_de_read(dev_priv,
-                                             dp_tp_ctl_reg(encoder, pipe_config)) & DP_TP_CTL_FEC_ENABLE;
-
-               pipe_config->infoframes.enable |=
-                       intel_hdmi_infoframes_enabled(encoder, pipe_config);
-               break;
-       default:
-               break;
+       ddi_mode = ddi_func_ctl & TRANS_DDI_MODE_SELECT_MASK;
+
+       if (ddi_mode == TRANS_DDI_MODE_SELECT_HDMI) {
+               intel_ddi_read_func_ctl_hdmi(encoder, pipe_config, ddi_func_ctl);
+       } else if (ddi_mode == TRANS_DDI_MODE_SELECT_DVI) {
+               intel_ddi_read_func_ctl_dvi(encoder, pipe_config, ddi_func_ctl);
+       } else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && !HAS_DP20(display)) {
+               intel_ddi_read_func_ctl_fdi(encoder, pipe_config, ddi_func_ctl);
+       } else if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_SST) {
+               intel_ddi_read_func_ctl_dp_sst(encoder, pipe_config, ddi_func_ctl);
+       } else if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_MST ||
+                  (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && HAS_DP20(display))) {
+               intel_ddi_read_func_ctl_dp_mst(encoder, pipe_config, ddi_func_ctl);
        }
 }