clk: qcom: Add support for Camera Clock Controller on QCS8300

The QCS8300 Camera clock controller is a derivative of SA8775P, but has
few additional clocks and offset differences. Hence, add support for
QCS8300 Camera clock controller by extending the SA8775P CamCC.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com>
Link: https://lore.kernel.org/r/20250327-qcs8300-mm-patches-v6-1-b3fbde2820a6@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/drivers/clk/qcom/camcc-sa8775p.c b/drivers/clk/qcom/camcc-sa8775p.c
index 11bd2e2348119d4238f2ad084a00983d2b219fbc..50e5a131261b0096b14a88315ce957348834a514 100644 (file)
--- a/drivers/clk/qcom/camcc-sa8775p.c
+++ b/drivers/clk/qcom/camcc-sa8775p.c
@@ -10,7 +10,7 @@
 #include <linux/pm_runtime.h>
 #include <linux/regmap.h>
 
-#include <dt-bindings/clock/qcom,sa8775p-camcc.h>
+#include <dt-bindings/clock/qcom,qcs8300-camcc.h>
 
 #include "clk-alpha-pll.h"
 #include "clk-branch.h"
@@ -1681,6 +1681,24 @@ static struct clk_branch cam_cc_sm_obs_clk = {
        },
 };
 
+static struct clk_branch cam_cc_titan_top_accu_shift_clk = {
+       .halt_reg = 0x131f0,
+       .halt_check = BRANCH_HALT_VOTED,
+       .clkr = {
+               .enable_reg = 0x131f0,
+               .enable_mask = BIT(0),
+               .hw.init = &(const struct clk_init_data) {
+                       .name = "cam_cc_titan_top_accu_shift_clk",
+                       .parent_hws = (const struct clk_hw*[]) {
+                               &cam_cc_xo_clk_src.clkr.hw,
+                       },
+                       .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
 static struct gdsc cam_cc_titan_top_gdsc = {
        .gdscr = 0x131bc,
        .en_rest_wait_val = 0x2,
@@ -1775,6 +1793,7 @@ static struct clk_regmap *cam_cc_sa8775p_clocks[] = {
        [CAM_CC_SLEEP_CLK_SRC] = &cam_cc_sleep_clk_src.clkr,
        [CAM_CC_SLOW_AHB_CLK_SRC] = &cam_cc_slow_ahb_clk_src.clkr,
        [CAM_CC_SM_OBS_CLK] = &cam_cc_sm_obs_clk.clkr,
+       [CAM_CC_TITAN_TOP_ACCU_SHIFT_CLK] = NULL,
        [CAM_CC_XO_CLK_SRC] = &cam_cc_xo_clk_src.clkr,
        [CAM_CC_QDSS_DEBUG_XO_CLK] = &cam_cc_qdss_debug_xo_clk.clkr,
 };
@@ -1811,6 +1830,7 @@ static const struct qcom_cc_desc cam_cc_sa8775p_desc = {
 };
 
 static const struct of_device_id cam_cc_sa8775p_match_table[] = {
+       { .compatible = "qcom,qcs8300-camcc" },
        { .compatible = "qcom,sa8775p-camcc" },
        { }
 };
@@ -1841,10 +1861,83 @@ static int cam_cc_sa8775p_probe(struct platform_device *pdev)
        clk_lucid_evo_pll_configure(&cam_cc_pll4, regmap, &cam_cc_pll4_config);
        clk_lucid_evo_pll_configure(&cam_cc_pll5, regmap, &cam_cc_pll5_config);
 
-       /* Keep some clocks always enabled */
-       qcom_branch_set_clk_en(regmap, 0x13194); /* CAM_CC_CAMNOC_XO_CLK */
-       qcom_branch_set_clk_en(regmap, 0x131ec); /* CAM_CC_GDSC_CLK */
-       qcom_branch_set_clk_en(regmap, 0x13208); /* CAM_CC_SLEEP_CLK */
+       if (device_is_compatible(&pdev->dev, "qcom,qcs8300-camcc")) {
+               cam_cc_camnoc_axi_clk_src.cmd_rcgr = 0x13154;
+               cam_cc_camnoc_axi_clk.halt_reg = 0x1316c;
+               cam_cc_camnoc_axi_clk.clkr.enable_reg = 0x1316c;
+               cam_cc_camnoc_dcd_xo_clk.halt_reg = 0x13174;
+               cam_cc_camnoc_dcd_xo_clk.clkr.enable_reg = 0x13174;
+
+               cam_cc_csi0phytimer_clk_src.cmd_rcgr = 0x15054;
+               cam_cc_csi1phytimer_clk_src.cmd_rcgr = 0x15078;
+               cam_cc_csi2phytimer_clk_src.cmd_rcgr = 0x15098;
+               cam_cc_csid_clk_src.cmd_rcgr = 0x13134;
+
+               cam_cc_mclk0_clk_src.cmd_rcgr = 0x15000;
+               cam_cc_mclk1_clk_src.cmd_rcgr = 0x1501c;
+               cam_cc_mclk2_clk_src.cmd_rcgr = 0x15038;
+
+               cam_cc_fast_ahb_clk_src.cmd_rcgr = 0x13104;
+               cam_cc_slow_ahb_clk_src.cmd_rcgr = 0x1311c;
+               cam_cc_xo_clk_src.cmd_rcgr = 0x131b8;
+               cam_cc_sleep_clk_src.cmd_rcgr = 0x131d4;
+
+               cam_cc_core_ahb_clk.halt_reg = 0x131b4;
+               cam_cc_core_ahb_clk.clkr.enable_reg = 0x131b4;
+
+               cam_cc_cpas_ahb_clk.halt_reg = 0x130f4;
+               cam_cc_cpas_ahb_clk.clkr.enable_reg = 0x130f4;
+               cam_cc_cpas_fast_ahb_clk.halt_reg = 0x130fc;
+               cam_cc_cpas_fast_ahb_clk.clkr.enable_reg = 0x130fc;
+
+               cam_cc_csi0phytimer_clk.halt_reg = 0x1506c;
+               cam_cc_csi0phytimer_clk.clkr.enable_reg = 0x1506c;
+               cam_cc_csi1phytimer_clk.halt_reg = 0x15090;
+               cam_cc_csi1phytimer_clk.clkr.enable_reg = 0x15090;
+               cam_cc_csi2phytimer_clk.halt_reg = 0x150b0;
+               cam_cc_csi2phytimer_clk.clkr.enable_reg = 0x150b0;
+               cam_cc_csid_clk.halt_reg = 0x1314c;
+               cam_cc_csid_clk.clkr.enable_reg = 0x1314c;
+               cam_cc_csid_csiphy_rx_clk.halt_reg = 0x15074;
+               cam_cc_csid_csiphy_rx_clk.clkr.enable_reg = 0x15074;
+               cam_cc_csiphy0_clk.halt_reg = 0x15070;
+               cam_cc_csiphy0_clk.clkr.enable_reg = 0x15070;
+               cam_cc_csiphy1_clk.halt_reg = 0x15094;
+               cam_cc_csiphy1_clk.clkr.enable_reg = 0x15094;
+               cam_cc_csiphy2_clk.halt_reg = 0x150b4;
+               cam_cc_csiphy2_clk.clkr.enable_reg = 0x150b4;
+
+               cam_cc_mclk0_clk.halt_reg = 0x15018;
+               cam_cc_mclk0_clk.clkr.enable_reg = 0x15018;
+               cam_cc_mclk1_clk.halt_reg = 0x15034;
+               cam_cc_mclk1_clk.clkr.enable_reg = 0x15034;
+               cam_cc_mclk2_clk.halt_reg = 0x15050;
+               cam_cc_mclk2_clk.clkr.enable_reg = 0x15050;
+               cam_cc_qdss_debug_xo_clk.halt_reg = 0x1319c;
+               cam_cc_qdss_debug_xo_clk.clkr.enable_reg = 0x1319c;
+
+               cam_cc_titan_top_gdsc.gdscr = 0x131a0;
+
+               cam_cc_sa8775p_clocks[CAM_CC_CCI_3_CLK] = NULL;
+               cam_cc_sa8775p_clocks[CAM_CC_CCI_3_CLK_SRC] = NULL;
+               cam_cc_sa8775p_clocks[CAM_CC_CSI3PHYTIMER_CLK] = NULL;
+               cam_cc_sa8775p_clocks[CAM_CC_CSI3PHYTIMER_CLK_SRC] = NULL;
+               cam_cc_sa8775p_clocks[CAM_CC_CSIPHY3_CLK] = NULL;
+               cam_cc_sa8775p_clocks[CAM_CC_MCLK3_CLK] = NULL;
+               cam_cc_sa8775p_clocks[CAM_CC_MCLK3_CLK_SRC] = NULL;
+               cam_cc_sa8775p_clocks[CAM_CC_TITAN_TOP_ACCU_SHIFT_CLK] =
+                               &cam_cc_titan_top_accu_shift_clk.clkr;
+
+               /* Keep some clocks always enabled */
+               qcom_branch_set_clk_en(regmap, 0x13178); /* CAM_CC_CAMNOC_XO_CLK */
+               qcom_branch_set_clk_en(regmap, 0x131d0); /* CAM_CC_GDSC_CLK */
+               qcom_branch_set_clk_en(regmap, 0x131ec); /* CAM_CC_SLEEP_CLK */
+       } else {
+               /* Keep some clocks always enabled */
+               qcom_branch_set_clk_en(regmap, 0x13194); /* CAM_CC_CAMNOC_XO_CLK */
+               qcom_branch_set_clk_en(regmap, 0x131ec); /* CAM_CC_GDSC_CLK */
+               qcom_branch_set_clk_en(regmap, 0x13208); /* CAM_CC_SLEEP_CLK */
+       }
 
        ret = qcom_cc_really_probe(&pdev->dev, &cam_cc_sa8775p_desc, regmap);