drm/i915/display/cnl+: Handle fused off DSC

DSC could be fused off, so not all GEN10+ platforms will support it.

Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Martin Peres <martin.peres@linux.intel.com>
Reviewed-by: Ramalingam C <ramalingam.c@intel.com>
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191026001323.216052-5-jose.souza@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 521ce23f38acfed8062f4bb4a79e745ba2cc6f2f..c24c6d3e4ab5123abc1fd99b30a0de9da1572153 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1888,6 +1888,9 @@ static bool intel_dp_source_supports_dsc(struct intel_dp *intel_dp,
 {
        struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 
+       if (!INTEL_INFO(dev_priv)->display.has_dsc)
+               return false;
+
        /* On TGL, DSC is supported on all Pipes */
        if (INTEL_GEN(dev_priv) >= 12)
                return true;

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 430da2d4082a26b5f3bdcf64d594cda17f60953d..1bb701d32a5da2c2c88a9d1bbc2f4aabf2b36db4 100644 (file)
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -737,6 +737,7 @@ static const struct intel_device_info intel_coffeelake_gt3_info = {
        GEN9_FEATURES, \
        GEN(10), \
        .ddb_size = 1024, \
+       .display.has_dsc = 1, \
        .has_coherent_ggtt = false, \
        GLK_COLORS
 

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 32a5371fff4f2250dba42c5abeb8aba76aac3011..5894e46ef68bab4d293bc82f495d97af50c55805 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7755,6 +7755,7 @@ enum {
 #define   SKL_DFSM_PIPE_B_DISABLE      (1 << 21)
 #define   SKL_DFSM_PIPE_C_DISABLE      (1 << 28)
 #define   TGL_DFSM_PIPE_D_DISABLE      (1 << 22)
+#define   CNL_DFSM_DISPLAY_DSC_DISABLE (1 << 7)
 
 #define SKL_DSSM                               _MMIO(0x51004)
 #define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz                (1 << 31)

diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index fa6464879142d7b46a86f2ce94a60024bd0566f3..a5b571364cf60a42e103e57b281b3e1371af30c2 100644 (file)
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -990,6 +990,10 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
 
                if (INTEL_GEN(dev_priv) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE))
                        info->display.has_csr = 0;
+
+               if (INTEL_GEN(dev_priv) >= 10 &&
+                   (dfsm & CNL_DFSM_DISPLAY_DSC_DISABLE))
+                       info->display.has_dsc = 0;
        }
 
        /* Initialize slice/subslice/EU info */

diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 64e4f1923c6881fc1b491cabfbbd4a94c66cb1d6..4bdf8a6cfb47518a5ee82411cafb13c020a0b1fa 100644 (file)
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -137,6 +137,7 @@ enum intel_ppgtt_type {
        func(has_ddi); \
        func(has_dp_mst); \
        func(has_dsb); \
+       func(has_dsc); \
        func(has_fbc); \
        func(has_gmch); \
        func(has_hdcp); \