drm/i915/xe2hpd: Do not program MBUS_DBOX BW credits

No display IP beyond Xe_LPD+ has "BW credits" bits in MBUS_DBOX_CTL
register. Restrict the programming only to Xe_LPD+.

BSpec: 49213
CC: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240430172850.1881525-13-radhakrishna.sripada@intel.com

diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index e6476aa621a7395a182673a8e47788ea9630257d..f85980aba25e6926ee0d250282494c3746ee1a80 100644 (file)
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -3616,7 +3616,7 @@ static void intel_mbus_dbox_update(struct intel_atomic_state *state)
        for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, new_dbuf_state->active_pipes) {
                u32 pipe_val = val;
 
-               if (DISPLAY_VER(i915) >= 14) {
+               if (DISPLAY_VER_FULL(i915) == IP_VER(14, 0)) {
                        if (xelpdp_is_only_pipe_per_dbuf_bank(crtc->pipe,
                                                              new_dbuf_state->active_pipes))
                                pipe_val |= MBUS_DBOX_BW_8CREDITS_MTL;