octeontx2-af: Set LMT_ENA bit for APR table entries

This patch enables the LMT line for a PF/VF by setting the
LMT_ENA bit in the APR_LMT_MAP_ENTRY_S structure.

Additionally, it simplifies the logic for calculating the
LMTST table index by consistently using the maximum
number of hw supported VFs (i.e., 256).

Fixes: 873a1e3d207a ("octeontx2-af: cn10k: Setting up lmtst map table").
Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com>
Signed-off-by: Geetha sowjanya <gakula@marvell.com>
Reviewed-by: Michal Swiatkowski <michal.swiatkowski@linux.intel.com>
Link: https://patch.msgid.link/20250521060834.19780-2-gakula@marvell.com
Signed-off-by: Paolo Abeni <pabeni@redhat.com>

diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c
index 7fa98aeb3663c02135350c8fd19290f26a9ae2e9..3838c04b78c221f405523d166eb36b8ded85d42c 100644 (file)
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c
@@ -15,13 +15,17 @@
 #define LMT_TBL_OP_WRITE       1
 #define LMT_MAP_TABLE_SIZE     (128 * 1024)
 #define LMT_MAPTBL_ENTRY_SIZE  16
+#define LMT_MAX_VFS            256
+
+#define LMT_MAP_ENTRY_ENA      BIT_ULL(20)
+#define LMT_MAP_ENTRY_LINES    GENMASK_ULL(18, 16)
 
 /* Function to perform operations (read/write) on lmtst map table */
 static int lmtst_map_table_ops(struct rvu *rvu, u32 index, u64 *val,
                               int lmt_tbl_op)
 {
        void __iomem *lmt_map_base;
-       u64 tbl_base;
+       u64 tbl_base, cfg;
 
        tbl_base = rvu_read64(rvu, BLKADDR_APR, APR_AF_LMT_MAP_BASE);
 
@@ -35,6 +39,13 @@ static int lmtst_map_table_ops(struct rvu *rvu, u32 index, u64 *val,
                *val = readq(lmt_map_base + index);
        } else {
                writeq((*val), (lmt_map_base + index));
+
+               cfg = FIELD_PREP(LMT_MAP_ENTRY_ENA, 0x1);
+               /* 2048 LMTLINES */
+               cfg |= FIELD_PREP(LMT_MAP_ENTRY_LINES, 0x6);
+
+               writeq(cfg, (lmt_map_base + (index + 8)));
+
                /* Flushing the AP interceptor cache to make APR_LMT_MAP_ENTRY_S
                 * changes effective. Write 1 for flush and read is being used as a
                 * barrier and sets up a data dependency. Write to 0 after a write
@@ -52,7 +63,7 @@ static int lmtst_map_table_ops(struct rvu *rvu, u32 index, u64 *val,
 #define LMT_MAP_TBL_W1_OFF  8
 static u32 rvu_get_lmtst_tbl_index(struct rvu *rvu, u16 pcifunc)
 {
-       return ((rvu_get_pf(pcifunc) * rvu->hw->total_vfs) +
+       return ((rvu_get_pf(pcifunc) * LMT_MAX_VFS) +
                (pcifunc & RVU_PFVF_FUNC_MASK)) * LMT_MAPTBL_ENTRY_SIZE;
 }