drm: omapdrm: dss: Expose DSS data in a dss_device structure

The anoonymous dss structure in dss.c is the top-level component in the
omapdss driver. As such it should store all internal instance-specific
data that is currently stored in global variables. This however requires
both naming the structure to pass it around functions, and accessing it
from various locations in the omapdss driver. While we could implement
get and set functions for every field that needs to be accessed outside
of dss.c, that would introduce overhead and complexity that we could
avoid by exposing the structure to internal components of the omapdss
driver. Do so to prepare for removal of global variables.

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>

diff --git a/drivers/gpu/drm/omapdrm/dss/dss.c b/drivers/gpu/drm/omapdrm/dss/dss.c
index d5490336e7c7935b2342bc1c92c9e18a273d52fa..245d8c0ae4619c5732a084f14e28f4f676b5f213 100644 (file)
--- a/drivers/gpu/drm/omapdrm/dss/dss.c
+++ b/drivers/gpu/drm/omapdrm/dss/dss.c
@@ -48,8 +48,6 @@
 #include "omapdss.h"
 #include "dss.h"
 
-#define DSS_SZ_REGS                    SZ_512
-
 struct dss_reg {
        u16 idx;
 };
@@ -90,32 +88,7 @@ struct dss_features {
        bool has_lcd_clk_src;
 };
 
-static struct {
-       struct platform_device *pdev;
-       void __iomem    *base;
-       struct regmap   *syscon_pll_ctrl;
-       u32             syscon_pll_ctrl_offset;
-
-       struct clk      *parent_clk;
-       struct clk      *dss_clk;
-       unsigned long   dss_clk_rate;
-
-       unsigned long   cache_req_pck;
-       unsigned long   cache_prate;
-       struct dispc_clock_info cache_dispc_cinfo;
-
-       enum dss_clk_source dsi_clk_source[MAX_NUM_DSI];
-       enum dss_clk_source dispc_clk_source;
-       enum dss_clk_source lcd_clk_source[MAX_DSS_LCD_MANAGERS];
-
-       bool            ctx_valid;
-       u32             ctx[DSS_SZ_REGS / sizeof(u32)];
-
-       const struct dss_features *feat;
-
-       struct dss_pll  *video1_pll;
-       struct dss_pll  *video2_pll;
-} dss;
+static struct dss_device dss;
 
 static const char * const dss_generic_clk_source_names[] = {
        [DSS_CLK_SRC_FCK]       = "FCK",

diff --git a/drivers/gpu/drm/omapdrm/dss/dss.h b/drivers/gpu/drm/omapdrm/dss/dss.h
index 7f3fa53304085785221404865daeb073cc38e3dc..257ff7c627648aaa06ce3e2ccd8e9091ad7e1f0b 100644 (file)
--- a/drivers/gpu/drm/omapdrm/dss/dss.h
+++ b/drivers/gpu/drm/omapdrm/dss/dss.h
@@ -235,6 +235,35 @@ struct dss_lcd_mgr_config {
 struct seq_file;
 struct platform_device;
 
+#define DSS_SZ_REGS                    SZ_512
+
+struct dss_device {
+       struct platform_device *pdev;
+       void __iomem    *base;
+       struct regmap   *syscon_pll_ctrl;
+       u32             syscon_pll_ctrl_offset;
+
+       struct clk      *parent_clk;
+       struct clk      *dss_clk;
+       unsigned long   dss_clk_rate;
+
+       unsigned long   cache_req_pck;
+       unsigned long   cache_prate;
+       struct dispc_clock_info cache_dispc_cinfo;
+
+       enum dss_clk_source dsi_clk_source[MAX_NUM_DSI];
+       enum dss_clk_source dispc_clk_source;
+       enum dss_clk_source lcd_clk_source[MAX_DSS_LCD_MANAGERS];
+
+       bool            ctx_valid;
+       u32             ctx[DSS_SZ_REGS / sizeof(u32)];
+
+       const struct dss_features *feat;
+
+       struct dss_pll  *video1_pll;
+       struct dss_pll  *video2_pll;
+};
+
 /* core */
 static inline int dss_set_min_bus_tput(struct device *dev, unsigned long tput)
 {