staging: mt7621-dts: gpio 8 and 9 are vendor specific

There are three pins that can be used for reset gpios.
As mentioned in the application note, there are two
possible way of wiring pcie reset:
* connect gpio19 to all pcie reset pins
* connect gpio19 to pcie0 reset and pick two other
gpios for pcie1 and pcie2

gpio7 and gpio8 may not be used as pcie reset and are
vendor specific. Hence, maintain common mt7621.dtsi with
only gpio19 which is common and make an overlay for gnubee
board which uses all gpio's as resets for pcie. After this
changes release gpios in driver code is not needed anymore.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Link: https://lore.kernel.org/r/20200321072650.7784-2-sergio.paracuellos@gmail.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/staging/mt7621-dts/gbpc1.dts b/drivers/staging/mt7621-dts/gbpc1.dts
index 1fb560ff059c83ff3a130c3b50bd20c0c67620d2..a7c0d3115d7264f36b25c563a9ccee03c9923e2d 100644 (file)
--- a/drivers/staging/mt7621-dts/gbpc1.dts
+++ b/drivers/staging/mt7621-dts/gbpc1.dts
@@ -114,6 +114,10 @@
 &pcie {
        pinctrl-names = "default";
        pinctrl-0 = <&pcie_pins>;
+
+       reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>,
+                       <&gpio 8 GPIO_ACTIVE_LOW>,
+                       <&gpio 7 GPIO_ACTIVE_LOW>;
        status = "okay";
 };
 

diff --git a/drivers/staging/mt7621-dts/mt7621.dtsi b/drivers/staging/mt7621-dts/mt7621.dtsi
index 10fb497cf81adcc8d5eca6b6ca3d8f665016466b..9e5cf68731bb040b88b0e8e5ac00bc09dce2767c 100644 (file)
--- a/drivers/staging/mt7621-dts/mt7621.dtsi
+++ b/drivers/staging/mt7621-dts/mt7621.dtsi
@@ -538,9 +538,7 @@
                phys = <&pcie0_phy 1>, <&pcie2_phy 0>;
                phy-names = "pcie-phy0", "pcie-phy2";
 
-               reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>,
-                               <&gpio 8 GPIO_ACTIVE_LOW>,
-                               <&gpio 7 GPIO_ACTIVE_LOW>;
+               reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
 
                pcie@0,0 {
                        reg = <0x0000 0 0 0 0>;