drm/xe/gsc: Introduce GSC FW

Add the basic definitions and init function. Same as HuC, GSC is only
supported on the media GT on MTL and newer platforms.
Note that the GSC requires submission resources which can't be allocated
during init (because we don't have the hwconfig yet), so it can't be
marked as loadable at the end of the init function. The allocation of
those resources will come in the patch that makes use of them to load
the FW.

v2: better comment, move num FWs define inside the enum (John)

Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Alan Previn <alan.previn.teres.alexis@intel.com>
Cc: John Harrison <John.C.Harrison@Intel.com>
Reviewed-by: John Harrison <John.C.Harrison@Intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index 05a90fd6c3c92d0a6ca31376d4965483d50987f7..184e2724ce7ba9ba0ac3f5695f978517d778a453 100644 (file)
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -58,6 +58,7 @@ xe-y += xe_bb.o \
        xe_force_wake.o \
        xe_ggtt.o \
        xe_gpu_scheduler.o \
+       xe_gsc.o \
        xe_gt.o \
        xe_gt_clock.o \
        xe_gt_debugfs.o \

diff --git a/drivers/gpu/drm/xe/xe_gsc.c b/drivers/gpu/drm/xe/xe_gsc.c
new file mode 100644 (file)
index 0000000..216f36c
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_gsc.c
@@ -0,0 +1,52 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+
+#include "xe_gsc.h"
+
+#include "xe_device.h"
+#include "xe_gt.h"
+#include "xe_gt_printk.h"
+#include "xe_uc_fw.h"
+
+static struct xe_gt *
+gsc_to_gt(struct xe_gsc *gsc)
+{
+       return container_of(gsc, struct xe_gt, uc.gsc);
+}
+
+int xe_gsc_init(struct xe_gsc *gsc)
+{
+       struct xe_gt *gt = gsc_to_gt(gsc);
+       struct xe_tile *tile = gt_to_tile(gt);
+       int ret;
+
+       gsc->fw.type = XE_UC_FW_TYPE_GSC;
+
+       /* The GSC uC is only available on the media GT */
+       if (tile->media_gt && (gt != tile->media_gt)) {
+               xe_uc_fw_change_status(&gsc->fw, XE_UC_FIRMWARE_NOT_SUPPORTED);
+               return 0;
+       }
+
+       /*
+        * Some platforms can have GuC but not GSC. That would cause
+        * xe_uc_fw_init(gsc) to return a "not supported" failure code and abort
+        * all firmware loading. So check for GSC being enabled before
+        * propagating the failure back up. That way the higher level will keep
+        * going and load GuC as appropriate.
+        */
+       ret = xe_uc_fw_init(&gsc->fw);
+       if (!xe_uc_fw_is_enabled(&gsc->fw))
+               return 0;
+       else if (ret)
+               goto out;
+
+       return 0;
+
+out:
+       xe_gt_err(gt, "GSC init failed with %d", ret);
+       return ret;
+}
+

diff --git a/drivers/gpu/drm/xe/xe_gsc.h b/drivers/gpu/drm/xe/xe_gsc.h
new file mode 100644 (file)
index 0000000..baa7f21
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_gsc.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+
+#ifndef _XE_GSC_H_
+#define _XE_GSC_H_
+
+#include "xe_gsc_types.h"
+
+int xe_gsc_init(struct xe_gsc *gsc);
+
+#endif

diff --git a/drivers/gpu/drm/xe/xe_gsc_types.h b/drivers/gpu/drm/xe/xe_gsc_types.h
new file mode 100644 (file)
index 0000000..135f156
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_gsc_types.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+
+#ifndef _XE_GSC_TYPES_H_
+#define _XE_GSC_TYPES_H_
+
+#include "xe_uc_fw_types.h"
+
+/**
+ * struct xe_gsc - GSC
+ */
+struct xe_gsc {
+       /** @fw: Generic uC firmware management */
+       struct xe_uc_fw fw;
+};
+
+#endif

diff --git a/drivers/gpu/drm/xe/xe_uc.c b/drivers/gpu/drm/xe/xe_uc.c
index 784f53c5f282f5817938c9a21ec8ef1dfb360644..b67154c78dff5ed74010fe7fe927a6b74d21afc5 100644 (file)
--- a/drivers/gpu/drm/xe/xe_uc.c
+++ b/drivers/gpu/drm/xe/xe_uc.c
@@ -6,6 +6,7 @@
 #include "xe_uc.h"
 
 #include "xe_device.h"
+#include "xe_gsc.h"
 #include "xe_gt.h"
 #include "xe_guc.h"
 #include "xe_guc_pc.h"
@@ -32,8 +33,8 @@ int xe_uc_init(struct xe_uc *uc)
        int ret;
 
        /*
-        * We call the GuC/HuC init functions even if GuC submission is off to
-        * correctly move our tracking of the FW state to "disabled".
+        * We call the GuC/HuC/GSC init functions even if GuC submission is off
+        * to correctly move our tracking of the FW state to "disabled".
         */
 
        ret = xe_guc_init(&uc->guc);
@@ -44,6 +45,10 @@ int xe_uc_init(struct xe_uc *uc)
        if (ret)
                goto err;
 
+       ret = xe_gsc_init(&uc->gsc);
+       if (ret)
+               goto err;
+
        if (!xe_device_uc_enabled(uc_to_xe(uc)))
                return 0;
 

diff --git a/drivers/gpu/drm/xe/xe_uc_fw.c b/drivers/gpu/drm/xe/xe_uc_fw.c
index 376fbc10c5ea40e166484570ecf614944ec898af..5eaf6ce0d025972a8dc9b0680ef892c710481645 100644 (file)
--- a/drivers/gpu/drm/xe/xe_uc_fw.c
+++ b/drivers/gpu/drm/xe/xe_uc_fw.c
@@ -158,11 +158,18 @@ XE_HUC_FIRMWARE_DEFS(XE_UC_MODULE_FIRMWARE,
 static struct xe_gt *
 __uc_fw_to_gt(struct xe_uc_fw *uc_fw, enum xe_uc_fw_type type)
 {
-       if (type == XE_UC_FW_TYPE_GUC)
-               return container_of(uc_fw, struct xe_gt, uc.guc.fw);
+       XE_WARN_ON(type >= XE_UC_FW_NUM_TYPES);
 
-       XE_WARN_ON(type != XE_UC_FW_TYPE_HUC);
-       return container_of(uc_fw, struct xe_gt, uc.huc.fw);
+       switch (type) {
+       case XE_UC_FW_TYPE_GUC:
+               return container_of(uc_fw, struct xe_gt, uc.guc.fw);
+       case XE_UC_FW_TYPE_HUC:
+               return container_of(uc_fw, struct xe_gt, uc.huc.fw);
+       case XE_UC_FW_TYPE_GSC:
+               return container_of(uc_fw, struct xe_gt, uc.gsc.fw);
+       default:
+               return NULL;
+       }
 }
 
 static struct xe_gt *uc_fw_to_gt(struct xe_uc_fw *uc_fw)
@@ -197,6 +204,14 @@ uc_fw_auto_select(struct xe_device *xe, struct xe_uc_fw *uc_fw)
        u32 count;
        int i;
 
+       /*
+        * GSC FW support is still not fully in place, so we're not defining
+        * the FW blob yet because we don't want the driver to attempt to load
+        * it until we're ready for it.
+        */
+       if (uc_fw->type == XE_UC_FW_TYPE_GSC)
+               return;
+
        xe_assert(xe, uc_fw->type < ARRAY_SIZE(blobs_all));
        entries = blobs_all[uc_fw->type].entries;
        count = blobs_all[uc_fw->type].count;

diff --git a/drivers/gpu/drm/xe/xe_uc_fw.h b/drivers/gpu/drm/xe/xe_uc_fw.h
index 1d1a0c156cdfd1ba45a86b6b287e5731b701d620..7feafe1695f9144e7a9660ff3e881171415538ee 100644 (file)
--- a/drivers/gpu/drm/xe/xe_uc_fw.h
+++ b/drivers/gpu/drm/xe/xe_uc_fw.h
@@ -96,8 +96,11 @@ static inline const char *xe_uc_fw_type_repr(enum xe_uc_fw_type type)
                return "GuC";
        case XE_UC_FW_TYPE_HUC:
                return "HuC";
+       case XE_UC_FW_TYPE_GSC:
+               return "GSC";
+       default:
+               return "uC";
        }
-       return "uC";
 }
 
 static inline enum xe_uc_fw_status

diff --git a/drivers/gpu/drm/xe/xe_uc_fw_types.h b/drivers/gpu/drm/xe/xe_uc_fw_types.h
index 46c801d8e954f89f76aae2d9449b3edba6e2acca..fc1de0cc93247f770b0be012b16f6255784c8fa4 100644 (file)
--- a/drivers/gpu/drm/xe/xe_uc_fw_types.h
+++ b/drivers/gpu/drm/xe/xe_uc_fw_types.h
@@ -55,9 +55,10 @@ enum xe_uc_fw_status {
 
 enum xe_uc_fw_type {
        XE_UC_FW_TYPE_GUC = 0,
-       XE_UC_FW_TYPE_HUC
+       XE_UC_FW_TYPE_HUC,
+       XE_UC_FW_TYPE_GSC,
+       XE_UC_FW_NUM_TYPES
 };
-#define XE_UC_FW_NUM_TYPES 2
 
 /**
  * struct xe_uc_fw_version - Version for XE micro controller firmware

diff --git a/drivers/gpu/drm/xe/xe_uc_types.h b/drivers/gpu/drm/xe/xe_uc_types.h
index 49bef6498b85ee7e8a22d84bd3584582fd89853f..9924e4484866356f7c726e5f0377c9160b2a3913 100644 (file)
--- a/drivers/gpu/drm/xe/xe_uc_types.h
+++ b/drivers/gpu/drm/xe/xe_uc_types.h
@@ -6,6 +6,7 @@
 #ifndef _XE_UC_TYPES_H_
 #define _XE_UC_TYPES_H_
 
+#include "xe_gsc_types.h"
 #include "xe_guc_types.h"
 #include "xe_huc_types.h"
 #include "xe_wopcm_types.h"
@@ -18,6 +19,8 @@ struct xe_uc {
        struct xe_guc guc;
        /** @huc: HuC */
        struct xe_huc huc;
+       /** @gsc: Graphics Security Controller */
+       struct xe_gsc gsc;
        /** @wopcm: WOPCM */
        struct xe_wopcm wopcm;
 };