arm64: dts: rockchip: add dsi controller nodes on rk3588

The RK3588 comes with two DSI2 controllers based on a new Synopsis IP.
Add the necessary nodes for them.

Signed-off-by: Heiko Stuebner <heiko.stuebner@cherry.de>
Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Tested-by: Sebastian Reichel <sebastian.reichel@collabora.com> # RK3588 EVB1
Link: https://lore.kernel.org/r/20250226140942.3825223-3-heiko@sntech.de
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
index 944721f314b1ad23156fc5a82370d2acd0a35bd1..548677de9a53cc41d2044a4533f35151e562bf5e 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
@@ -6,6 +6,7 @@
 #include <dt-bindings/clock/rockchip,rk3588-cru.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/phy/phy.h>
 #include <dt-bindings/power/rk3588-power.h>
 #include <dt-bindings/reset/rockchip,rk3588-cru.h>
 #include <dt-bindings/phy/phy.h>
@@ -1421,6 +1422,62 @@
                status = "disabled";
        };
 
+       dsi0: dsi@fde20000 {
+               compatible = "rockchip,rk3588-mipi-dsi2";
+               reg = <0x0 0xfde20000 0x0 0x10000>;
+               interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH 0>;
+               clocks = <&cru PCLK_DSIHOST0>, <&cru CLK_DSIHOST0>;
+               clock-names = "pclk", "sys";
+               resets = <&cru SRST_P_DSIHOST0>;
+               reset-names = "apb";
+               power-domains = <&power RK3588_PD_VOP>;
+               phys = <&mipidcphy0 PHY_TYPE_DPHY>;
+               phy-names = "dcphy";
+               rockchip,grf = <&vop_grf>;
+               status = "disabled";
+
+               ports {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       dsi0_in: port@0 {
+                               reg = <0>;
+                       };
+
+                       dsi0_out: port@1 {
+                               reg = <1>;
+                       };
+               };
+       };
+
+       dsi1: dsi@fde30000 {
+               compatible = "rockchip,rk3588-mipi-dsi2";
+               reg = <0x0 0xfde30000 0x0 0x10000>;
+               interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH 0>;
+               clocks = <&cru PCLK_DSIHOST1>, <&cru CLK_DSIHOST1>;
+               clock-names = "pclk", "sys";
+               resets = <&cru SRST_P_DSIHOST1>;
+               reset-names = "apb";
+               power-domains = <&power RK3588_PD_VOP>;
+               phys = <&mipidcphy1 PHY_TYPE_DPHY>;
+               phy-names = "dcphy";
+               rockchip,grf = <&vop_grf>;
+               status = "disabled";
+
+               ports {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       dsi1_in: port@0 {
+                               reg = <0>;
+                       };
+
+                       dsi1_out: port@1 {
+                               reg = <1>;
+                       };
+               };
+       };
+
        hdmi0: hdmi@fde80000 {
                compatible = "rockchip,rk3588-dw-hdmi-qp";
                reg = <0x0 0xfde80000 0x0 0x20000>;