drm/amdgpu: Add debugfs interface to set arbitrary sclk for navi14 (v2)

add debugfs interface amdgpu_force_sclk
to set arbitrary sclk for navi14

v2: Add lock

Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
index abc148280ba5a2c873794a30d0ad5beb7230a568..831f70dc8b598272e98e9394de545736a1db4531 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
@@ -1257,9 +1257,43 @@ failure:
        return 0;
 }
 
+static int amdgpu_debugfs_sclk_set(void *data, u64 val)
+{
+       int ret = 0;
+       uint32_t max_freq, min_freq;
+       struct amdgpu_device *adev = (struct amdgpu_device *)data;
+
+       if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
+               return -EINVAL;
+
+       ret = pm_runtime_get_sync(adev->ddev->dev);
+       if (ret < 0)
+               return ret;
+
+       if (is_support_sw_smu(adev)) {
+               ret = smu_get_dpm_freq_range(&adev->smu, SMU_SCLK, &min_freq, &max_freq, true);
+               if (ret || val > max_freq || val < min_freq)
+                       return -EINVAL;
+               ret = smu_set_soft_freq_range(&adev->smu, SMU_SCLK, (uint32_t)val, (uint32_t)val, true);
+       } else {
+               return 0;
+       }
+
+       pm_runtime_mark_last_busy(adev->ddev->dev);
+       pm_runtime_put_autosuspend(adev->ddev->dev);
+
+       if (ret)
+               return -EINVAL;
+
+       return 0;
+}
+
 DEFINE_SIMPLE_ATTRIBUTE(fops_ib_preempt, NULL,
                        amdgpu_debugfs_ib_preempt, "%llu\n");
 
+DEFINE_SIMPLE_ATTRIBUTE(fops_sclk_set, NULL,
+                       amdgpu_debugfs_sclk_set, "%llu\n");
+
 int amdgpu_debugfs_init(struct amdgpu_device *adev)
 {
        int r, i;
@@ -1273,6 +1307,15 @@ int amdgpu_debugfs_init(struct amdgpu_device *adev)
                return -EIO;
        }
 
+       adev->smu.debugfs_sclk =
+               debugfs_create_file("amdgpu_force_sclk", 0200,
+                                   adev->ddev->primary->debugfs_root, adev,
+                                   &fops_sclk_set);
+       if (!(adev->smu.debugfs_sclk)) {
+               DRM_ERROR("unable to create amdgpu_set_sclk debugsfs file\n");
+               return -EIO;
+       }
+
        /* Register debugfs entries for amdgpu_ttm */
        r = amdgpu_ttm_debugfs_init(adev);
        if (r) {

diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index c8e72c73c3b6425afcfc66c503f6c5d2dccc6748..657a6f17e91f350a2e1a8b337dac29b5152784c7 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -372,6 +372,9 @@ struct smu_context
        struct amd_pp_display_configuration  *display_config;
        struct smu_baco_context         smu_baco;
        void *od_settings;
+#if defined(CONFIG_DEBUG_FS)
+       struct dentry                   *debugfs_sclk;
+#endif
 
        uint32_t pstate_sclk;
        uint32_t pstate_mclk;