drm/amd/display: use even ODM slice width for two pixels per container
authorWenjing Liu <wenjing.liu@amd.com>
Wed, 17 Apr 2024 19:23:08 +0000 (15:23 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Fri, 14 Jun 2024 20:17:13 +0000 (16:17 -0400)
[why]
When optc uses two pixel per container, each ODM slice width must be an
even number.

[how]
If ODM slice width is odd number increase it by 1.

Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/spl/dc_spl.c
drivers/gpu/drm/amd/display/dc/spl/dc_spl_types.h

index 2836f28fa3af05b9fb907e0f7e4254bd238bcfc6..9c6171e90163cc8a9616f8de02b367070062e1b3 100644 (file)
@@ -173,6 +173,9 @@ static struct spl_rect calculate_odm_slice_in_timing_active(struct spl_in *spl_i
        int odm_slice_width = h_active / odm_slice_count;
        struct spl_rect odm_rec;
 
+       if (spl_in->basic_out.use_two_pixels_per_container && (odm_slice_width % 2))
+               odm_slice_width++;
+
        odm_rec.x = odm_slice_width * odm_slice_idx;
        odm_rec.width = is_last_odm_slice ?
                        /* last slice width is the reminder of h_active */
index a8f7fccfa16b323cc475f3cf99e0732eb1a80903..49c866a558f6c25b8081f1535cf8b8b4fbd8d571 100644 (file)
@@ -441,6 +441,7 @@ struct basic_out {
        bool always_scale;      // Is always scale enabled? Required for getting SCL_MODE
        int max_downscale_src_width; // Required to get optimal no of taps
        bool alpha_en;
+       bool use_two_pixels_per_container;
 };
 enum explicit_sharpness        {
        SHARPNESS_LOW = 0,