e1000e: Add support for the next LOM generation
authorSasha Neftin <sasha.neftin@intel.com>
Thu, 29 Sep 2022 08:08:59 +0000 (11:08 +0300)
committerTony Nguyen <anthony.l.nguyen@intel.com>
Wed, 2 Nov 2022 18:00:10 +0000 (11:00 -0700)
Add devices IDs for the next LOM generations that will be available on the
next Intel Client platforms.
This patch provides the initial support for these devices.

Signed-off-by: Sasha Neftin <sasha.neftin@intel.com>
Tested-by: Naama Meir <naamax.meir@linux.intel.com>
Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
drivers/net/ethernet/intel/e1000e/ethtool.c
drivers/net/ethernet/intel/e1000e/hw.h
drivers/net/ethernet/intel/e1000e/ich8lan.c
drivers/net/ethernet/intel/e1000e/netdev.c
drivers/net/ethernet/intel/e1000e/ptp.c

index 51a5afe9df2fe9cf07a508861ea60756d128f372..59e82d131d88fad3dab0b59476e151ffdef26f7a 100644 (file)
@@ -908,6 +908,7 @@ static int e1000_reg_test(struct e1000_adapter *adapter, u64 *data)
        case e1000_pch_adp:
        case e1000_pch_mtp:
        case e1000_pch_lnp:
+       case e1000_pch_ptp:
                mask |= BIT(18);
                break;
        default:
@@ -1575,6 +1576,7 @@ static void e1000_loopback_cleanup(struct e1000_adapter *adapter)
        case e1000_pch_adp:
        case e1000_pch_mtp:
        case e1000_pch_lnp:
+       case e1000_pch_ptp:
                fext_nvm11 = er32(FEXTNVM11);
                fext_nvm11 &= ~E1000_FEXTNVM11_DISABLE_MULR_FIX;
                ew32(FEXTNVM11, fext_nvm11);
index bcf680e838113ddfd9d73a712fb94eac772ea343..29f9fae35f426bae2e9065ef523aa2d9847df036 100644 (file)
@@ -114,6 +114,14 @@ struct e1000_hw;
 #define E1000_DEV_ID_PCH_LNP_I219_V20          0x550F
 #define E1000_DEV_ID_PCH_LNP_I219_LM21         0x5510
 #define E1000_DEV_ID_PCH_LNP_I219_V21          0x5511
+#define E1000_DEV_ID_PCH_ARL_I219_LM24         0x57A0
+#define E1000_DEV_ID_PCH_ARL_I219_V24          0x57A1
+#define E1000_DEV_ID_PCH_PTP_I219_LM25         0x57B3
+#define E1000_DEV_ID_PCH_PTP_I219_V25          0x57B4
+#define E1000_DEV_ID_PCH_PTP_I219_LM26         0x57B5
+#define E1000_DEV_ID_PCH_PTP_I219_V26          0x57B6
+#define E1000_DEV_ID_PCH_PTP_I219_LM27         0x57B7
+#define E1000_DEV_ID_PCH_PTP_I219_V27          0x57B8
 
 #define E1000_REVISION_4       4
 
@@ -141,6 +149,7 @@ enum e1000_mac_type {
        e1000_pch_adp,
        e1000_pch_mtp,
        e1000_pch_lnp,
+       e1000_pch_ptp,
 };
 
 enum e1000_media_type {
index e8f7cb9d87241cb42768b73c3cb787807c553afe..0c7fd10312c8d169055a6762b32dfa31ba558310 100644 (file)
@@ -322,6 +322,7 @@ static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
        case e1000_pch_adp:
        case e1000_pch_mtp:
        case e1000_pch_lnp:
+       case e1000_pch_ptp:
                if (e1000_phy_is_accessible_pchlan(hw))
                        break;
 
@@ -468,6 +469,7 @@ static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
                case e1000_pch_adp:
                case e1000_pch_mtp:
                case e1000_pch_lnp:
+               case e1000_pch_ptp:
                        /* In case the PHY needs to be in mdio slow mode,
                         * set slow mode and try to get the PHY id again.
                         */
@@ -714,6 +716,7 @@ static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
        case e1000_pch_adp:
        case e1000_pch_mtp:
        case e1000_pch_lnp:
+       case e1000_pch_ptp:
        case e1000_pchlan:
                /* check management mode */
                mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
@@ -1681,6 +1684,7 @@ static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
        case e1000_pch_adp:
        case e1000_pch_mtp:
        case e1000_pch_lnp:
+       case e1000_pch_ptp:
                rc = e1000_init_phy_params_pchlan(hw);
                break;
        default:
@@ -2137,6 +2141,7 @@ static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
        case e1000_pch_adp:
        case e1000_pch_mtp:
        case e1000_pch_lnp:
+       case e1000_pch_ptp:
                sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
                break;
        default:
@@ -3182,6 +3187,7 @@ static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
        case e1000_pch_adp:
        case e1000_pch_mtp:
        case e1000_pch_lnp:
+       case e1000_pch_ptp:
                bank1_offset = nvm->flash_bank_size;
                act_offset = E1000_ICH_NVM_SIG_WORD;
 
@@ -4122,6 +4128,7 @@ static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
        case e1000_pch_adp:
        case e1000_pch_mtp:
        case e1000_pch_lnp:
+       case e1000_pch_ptp:
                word = NVM_COMPAT;
                valid_csum_mask = NVM_COMPAT_VALID_CSUM;
                break;
index 4dc862399f0c1135797a2a067208782a8c36a01b..edc8aa9822ee55f564c33a166f409cb2cc57d31c 100644 (file)
@@ -3553,6 +3553,7 @@ s32 e1000e_get_base_timinca(struct e1000_adapter *adapter, u32 *timinca)
        case e1000_pch_adp:
        case e1000_pch_mtp:
        case e1000_pch_lnp:
+       case e1000_pch_ptp:
                if (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI) {
                        /* Stable 24MHz frequency */
                        incperiod = INCPERIOD_24MHZ;
@@ -4068,6 +4069,7 @@ void e1000e_reset(struct e1000_adapter *adapter)
        case e1000_pch_adp:
        case e1000_pch_mtp:
        case e1000_pch_lnp:
+       case e1000_pch_ptp:
                fc->refresh_time = 0xFFFF;
                fc->pause_time = 0xFFFF;
 
@@ -7914,6 +7916,14 @@ static const struct pci_device_id e1000_pci_tbl[] = {
        { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LNP_I219_V20), board_pch_mtp },
        { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LNP_I219_LM21), board_pch_mtp },
        { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LNP_I219_V21), board_pch_mtp },
+       { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ARL_I219_LM24), board_pch_mtp },
+       { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ARL_I219_V24), board_pch_mtp },
+       { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_PTP_I219_LM25), board_pch_mtp },
+       { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_PTP_I219_V25), board_pch_mtp },
+       { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_PTP_I219_LM26), board_pch_mtp },
+       { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_PTP_I219_V26), board_pch_mtp },
+       { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_PTP_I219_LM27), board_pch_mtp },
+       { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_PTP_I219_V27), board_pch_mtp },
 
        { 0, 0, 0, 0, 0, 0, 0 } /* terminate list */
 };
index 6e5a1720e6cd663a75b1e57d57886c1805c77312..def4566a916f31b4652201e2a23d979722686b36 100644 (file)
@@ -287,6 +287,7 @@ void e1000e_ptp_init(struct e1000_adapter *adapter)
        case e1000_pch_adp:
        case e1000_pch_mtp:
        case e1000_pch_lnp:
+       case e1000_pch_ptp:
                if ((hw->mac.type < e1000_pch_lpt) ||
                    (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI)) {
                        adapter->ptp_clock_info.max_adj = 24000000 - 1;