Merge tag 'armsoc-fixes-nc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm...
authorLinus Torvalds <torvalds@linux-foundation.org>
Thu, 21 Jan 2016 01:44:16 +0000 (17:44 -0800)
committerLinus Torvalds <torvalds@linux-foundation.org>
Thu, 21 Jan 2016 01:44:16 +0000 (17:44 -0800)
Pull non-urgent ARM SoC fixes from Olof Johansson:
 "As usual, we queue up a few fixes that don't seem urgent enough to go
  in through -rc.

   - MAINTAINERS updates to add a list for brcmstb and fix a typo
   - A handful of fixes for OMAP 81xx, a recently resurrected platform
     so these can't be considered real regressions and thus got queued.
   - A couple of other small fixes for scoop, sa1100 and davinci"

* tag 'armsoc-fixes-nc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
  ARM: OMAP2+: Fix randconfig build warning for dm814_pllss_data
  ARM: sa1100/simpad: Be sure to clamp return value
  ARM: scoop: Be sure to clamp return value
  ARM: davinci: fix a problematic usage of WARN()
  ARM: davinci: only select WT cache if cache is enabled
  ARM: OMAP2+: Remove useless check for legacy booting for dm814x
  ARM: OMAP2+: Enable GPIO for dm814x
  ARM: dts: Fix dm814x pinctrl address and mask
  ARM: dts: Fix dm8148 control modules ranges
  ARM: OMAP2+: Fix timer entries for dm814x
  ARM: dts: Fix some mux and divider clocks to get dm814x-evm booting
  ARM: OMAP2+: Add DPPLS clock manager for dm814x
  clk: ti: Add few dm814x clock aliases
  ARM: dts: Fix dm814x entries for pllss and prcm
  MAINTAINERS: gpio-brcmstb: Remove stray '>'
  MAINTAINERS: brcmstb: Include Broadcom internal mailing-list

13 files changed:
MAINTAINERS
arch/arm/boot/dts/dm814x-clocks.dtsi
arch/arm/boot/dts/dm814x.dtsi
arch/arm/common/scoop.c
arch/arm/mach-davinci/Kconfig
arch/arm/mach-davinci/board-dm355-evm.c
arch/arm/mach-davinci/board-dm355-leopard.c
arch/arm/mach-omap2/io.c
arch/arm/mach-omap2/omap_hwmod_81xx_data.c
arch/arm/mach-omap2/prm_common.c
arch/arm/mach-sa1100/simpad.c
drivers/clk/ti/clk-814x.c
include/linux/clk/ti.h

index 66662b80e7111cad009a002a7fdebf6b39791882..5affae6e99b87d990497fff00046ebb07624a4e8 100644 (file)
@@ -2377,6 +2377,7 @@ M:        Brian Norris <computersforpeace@gmail.com>
 M:     Gregory Fong <gregory.0xf0@gmail.com>
 M:     Florian Fainelli <f.fainelli@gmail.com>
 L:     linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
+L:     bcm-kernel-feedback-list@broadcom.com
 T:     git git://github.com/broadcom/stblinux.git
 S:     Maintained
 F:     arch/arm/mach-bcm/*brcmstb*
@@ -2450,7 +2451,7 @@ N:        bcm88312
 
 BROADCOM BRCMSTB GPIO DRIVER
 M:     Gregory Fong <gregory.0xf0@gmail.com>
-L:     bcm-kernel-feedback-list@broadcom.com>
+L:     bcm-kernel-feedback-list@broadcom.com
 S:     Supported
 F:     drivers/gpio/gpio-brcmstb.c
 F:     Documentation/devicetree/bindings/gpio/brcm,brcmstb-gpio.txt
index ef1e8e7a6cc66810f1ae436b3d72a4d867f6e3e4..26001585673add86c25b11874d4a98c3a55ec691 100644 (file)
@@ -4,25 +4,74 @@
  * published by the Free Software Foundation.
  */
 
+&pllss_clocks {
+       timer1_fck: timer1_fck {
+               #clock-cells = <0>;
+               compatible = "ti,mux-clock";
+               clocks = <&sysclk18_ck &aud_clkin0_ck &aud_clkin1_ck
+                         &aud_clkin2_ck &devosc_ck &auxosc_ck &tclkin_ck>;
+               ti,bit-shift = <3>;
+               reg = <0x2e0>;
+       };
+
+       timer2_fck: timer2_fck {
+               #clock-cells = <0>;
+               compatible = "ti,mux-clock";
+               clocks = <&sysclk18_ck &aud_clkin0_ck &aud_clkin1_ck
+                         &aud_clkin2_ck &devosc_ck &auxosc_ck &tclkin_ck>;
+               ti,bit-shift = <6>;
+               reg = <0x2e0>;
+       };
+
+       sysclk18_ck: sysclk18_ck {
+               #clock-cells = <0>;
+               compatible = "ti,mux-clock";
+               clocks = <&rtcosc_ck>, <&rtcdivider_ck>;
+               ti,bit-shift = <0>;
+               reg = <0x02f0>;
+       };
+};
+
 &scm_clocks {
+       devosc_ck: devosc_ck {
+               #clock-cells = <0>;
+               compatible = "ti,mux-clock";
+               clocks = <&virt_20000000_ck>, <&virt_19200000_ck>;
+               ti,bit-shift = <21>;
+               reg = <0x0040>;
+       };
 
-       tclkin_ck: tclkin_ck {
+       /* Optional auxosc, 20 - 30 MHz range, assume 27 MHz by default */
+       auxosc_ck: auxosc_ck {
+               #clock-cells = <0>;
+               compatible = "fixed-clock";
+               clock-frequency = <27000000>;
+       };
+
+       /* Optional 32768Hz crystal or clock on RTCOSC pins */
+       rtcosc_ck: rtcosc_ck {
                #clock-cells = <0>;
                compatible = "fixed-clock";
                clock-frequency = <32768>;
        };
 
-       devosc_ck: devosc_ck {
+       /* Optional external clock on TCLKIN pin, set rate in baord dts file */
+       tclkin_ck: tclkin_ck {
+               #clock-cells = <0>;
+               compatible = "fixed-clock";
+               clock-frequency = <0>;
+       };
+
+       virt_20000000_ck: virt_20000000_ck {
                #clock-cells = <0>;
                compatible = "fixed-clock";
                clock-frequency = <20000000>;
        };
 
-       /* Optional auxosc, 20 - 30 MHz range, assume 27 MHz by default */
-       auxosc_ck: auxosc_ck {
+       virt_19200000_ck: virt_19200000_ck {
                #clock-cells = <0>;
                compatible = "fixed-clock";
-               clock-frequency = <27000000>;
+               clock-frequency = <19200000>;
        };
 
        mpu_ck: mpu_ck {
                clock-frequency = <48000000>;
        };
 
-       sysclk18_ck: sysclk18_ck {
-               #clock-cells = <0>;
-               compatible = "fixed-clock";
-               clock-frequency = <32768>;
-       };
-
         cpsw_125mhz_gclk: cpsw_125mhz_gclk {
                #clock-cells = <0>;
                compatible = "fixed-clock";
 
 };
 
-&pllss_clocks {
+&prcm_clocks {
+       osc_src_ck: osc_src_ck {
+               #clock-cells = <0>;
+               compatible = "fixed-factor-clock";
+               clocks = <&devosc_ck>;
+               clock-mult = <1>;
+               clock-div = <1>;
+       };
+
+       mpu_clksrc_ck: mpu_clksrc_ck {
+               #clock-cells = <0>;
+               compatible = "ti,mux-clock";
+               clocks = <&devosc_ck>, <&rtcdivider_ck>;
+               ti,bit-shift = <0>;
+               reg = <0x0040>;
+       };
+
+       /* Fixed divider clock 0.0016384 * devosc */
+       rtcdivider_ck: rtcdivider_ck {
+               #clock-cells = <0>;
+               compatible = "fixed-factor-clock";
+               clocks = <&devosc_ck>;
+               clock-mult = <128>;
+               clock-div = <78125>;
+       };
 
        aud_clkin0_ck: aud_clkin0_ck {
                #clock-cells = <0>;
                compatible = "fixed-clock";
                clock-frequency = <20000000>;
        };
-
-       timer1_mux_ck: timer1_mux_ck {
-               #clock-cells = <0>;
-               compatible = "ti,mux-clock";
-               clocks = <&sysclk18_ck &aud_clkin0_ck &aud_clkin1_ck
-                         &aud_clkin2_ck &devosc_ck &auxosc_ck &tclkin_ck>;
-               ti,bit-shift = <3>;
-               reg = <0x2e0>;
-       };
-
-       timer2_mux_ck: timer2_mux_ck {
-               #clock-cells = <0>;
-               compatible = "ti,mux-clock";
-               clocks = <&sysclk18_ck &aud_clkin0_ck &aud_clkin1_ck
-                         &aud_clkin2_ck &devosc_ck &auxosc_ck &tclkin_ck>;
-               ti,bit-shift = <6>;
-               reg = <0x2e0>;
-       };
 };
index 7988b42e57640584df8f8c459f6ff6652e325ed6..09a8d88bde2360de6f44fef57fc52ec122a2223e 100644 (file)
                ti,hwmods = "l3_main";
 
                /*
-                * See TRM "Table 1-317. L4LS Instance Summary", just deduct
-                * 0x1000 from the 1-317 addresses to get the device address
+                * See TRM "Table 1-317. L4LS Instance Summary" for hints.
+                * It shows the module target agent registers though, so the
+                * actual device is typically 0x1000 before the target agent
+                * except in cases where the module is larger than 0x1000.
                 */
                l4ls: l4ls@48000000 {
                        compatible = "ti,dm814-l4ls", "simple-bus";
 
                        control: control@140000 {
                                compatible = "ti,dm814-scm", "simple-bus";
-                               reg = <0x140000 0x16d000>;
+                               reg = <0x140000 0x20000>;
                                #address-cells = <1>;
                                #size-cells = <1>;
-                               ranges = <0 0x160000 0x16d000>;
+                               ranges = <0 0x140000 0x20000>;
 
                                scm_conf: scm_conf@0 {
                                        compatible = "syscon";
                                        };
                                };
 
+                               /*
+                                * Note that silicon revision 2.1 and older
+                                * require input enabled (bit 18 set) for all
+                                * 3.3V I/Os to avoid cumulative hardware damage.
+                                * For more info, see errata advisory 2.1.87.
+                                * We leave bit 18 out of function-mask and rely
+                                * on the bootloader for it.
+                                */
                                pincntl: pinmux@800 {
                                        compatible = "pinctrl-single";
-                                       reg = <0x800 0xc38>;
+                                       reg = <0x800 0x438>;
                                        #address-cells = <1>;
                                        #size-cells = <0>;
                                        pinctrl-single,register-width = <32>;
-                                       pinctrl-single,function-mask = <0x300ff>;
+                                       pinctrl-single,function-mask = <0x307ff>;
                                };
                        };
 
                        prcm: prcm@180000 {
                                compatible = "ti,dm814-prcm", "simple-bus";
-                               reg = <0x180000 0x4000>;
+                               reg = <0x180000 0x2000>;
+                               #address-cells = <1>;
+                               #size-cells = <1>;
+                               ranges = <0 0x180000 0x2000>;
 
                                prcm_clocks: clocks {
                                        #address-cells = <1>;
                                };
                        };
 
+                       /* See TRM PLL_SUBSYS_BASE and "PLLSS Registers" */
                        pllss: pllss@1c5000 {
                                compatible = "ti,dm814-pllss", "simple-bus";
-                               reg = <0x1c5000 0x2000>;
+                               reg = <0x1c5000 0x1000>;
+                               #address-cells = <1>;
+                               #size-cells = <1>;
+                               ranges = <0 0x1c5000 0x1000>;
 
                                pllss_clocks: clocks {
                                        #address-cells = <1>;
index 45f4c21e393c1992bfdcc980e859fe081968dffd..e0df333202b81d8fea565353e391c3c043e12fc0 100644 (file)
@@ -84,7 +84,7 @@ static int scoop_gpio_get(struct gpio_chip *chip, unsigned offset)
        struct scoop_dev *sdev = container_of(chip, struct scoop_dev, gpio);
 
        /* XXX: I'm unsure, but it seems so */
-       return ioread16(sdev->base + SCOOP_GPRR) & (1 << (offset + 1));
+       return !!(ioread16(sdev->base + SCOOP_GPRR) & (1 << (offset + 1)));
 }
 
 static int scoop_gpio_direction_input(struct gpio_chip *chip,
index dd8f5312b2c0e5d15e38b42dbaaee88a4718ce61..bcaf1d0255057ed02353b21028064001e0a1c2ef 100644 (file)
@@ -34,7 +34,8 @@ config ARCH_DAVINCI_DA830
        bool "DA830/OMAP-L137/AM17x based system"
        depends on !ARCH_DAVINCI_DMx || AUTO_ZRELADDR
        select ARCH_DAVINCI_DA8XX
-       select CPU_DCACHE_WRITETHROUGH # needed on silicon revs 1.0, 1.1
+       # needed on silicon revs 1.0, 1.1:
+       select CPU_DCACHE_WRITETHROUGH if !CPU_DCACHE_DISABLE
        select CP_INTC
 
 config ARCH_DAVINCI_DA850
index c71dd9982f03a1eadf5e4b75b2d8a284f343bda8..1844076f64030c94ecd13f31b7c6ff85bd9deae1 100644 (file)
@@ -384,9 +384,7 @@ static __init void dm355_evm_init(void)
        dm355evm_dm9000_rsrc[2].start = gpio_to_irq(1);
 
        aemif = clk_get(&dm355evm_dm9000.dev, "aemif");
-       if (IS_ERR(aemif))
-               WARN("%s: unable to get AEMIF clock\n", __func__);
-       else
+       if (!WARN(IS_ERR(aemif), "unable to get AEMIF clock\n"))
                clk_prepare_enable(aemif);
 
        platform_add_devices(davinci_evm_devices,
index 680a7a2d9102761c1cdadb1d125b45d92b65d9c0..284ff27c1b32228d7b9cdcf1dd6cade90b8bd65d 100644 (file)
@@ -242,9 +242,7 @@ static __init void dm355_leopard_init(void)
        dm355leopard_dm9000_rsrc[2].start = gpio_to_irq(9);
 
        aemif = clk_get(&dm355leopard_dm9000.dev, "aemif");
-       if (IS_ERR(aemif))
-               WARN("%s: unable to get AEMIF clock\n", __func__);
-       else
+       if (!WARN(IS_ERR(aemif), "unable to get AEMIF clock\n"))
                clk_prepare_enable(aemif);
 
        platform_add_devices(davinci_leopard_devices,
index 3eaeaca5da05f95fffe03d8927bc0b9ec0f63ef5..3c87e40650cf374daf3083437c8ec614fdbc136e 100644 (file)
@@ -612,8 +612,7 @@ void __init ti814x_init_early(void)
        ti814x_clockdomains_init();
        dm814x_hwmod_init();
        omap_hwmod_init_postsetup();
-       if (of_have_populated_dt())
-               omap_clk_soc_init = dm814x_dt_clk_init;
+       omap_clk_soc_init = dm814x_dt_clk_init;
 }
 
 void __init ti816x_init_early(void)
index 6256052893ec7b1453c3d0afb6e392c321040567..1b96cdfd15586c58c63286cbe62387926127f457 100644 (file)
@@ -599,7 +599,7 @@ static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
 static struct omap_hwmod dm814x_timer1_hwmod = {
        .name           = "timer1",
        .clkdm_name     = "alwon_l3s_clkdm",
-       .main_clk       = "timer_sys_ck",
+       .main_clk       = "timer1_fck",
        .dev_attr       = &capability_alwon_dev_attr,
        .class          = &dm816x_timer_hwmod_class,
        .flags          = HWMOD_NO_IDLEST,
@@ -608,7 +608,7 @@ static struct omap_hwmod dm814x_timer1_hwmod = {
 static struct omap_hwmod_ocp_if dm814x_l4_ls__timer1 = {
        .master         = &dm81xx_l4_ls_hwmod,
        .slave          = &dm814x_timer1_hwmod,
-       .clk            = "timer_sys_ck",
+       .clk            = "timer1_fck",
        .user           = OCP_USER_MPU,
 };
 
@@ -636,7 +636,7 @@ static struct omap_hwmod_ocp_if dm816x_l4_ls__timer1 = {
 static struct omap_hwmod dm814x_timer2_hwmod = {
        .name           = "timer2",
        .clkdm_name     = "alwon_l3s_clkdm",
-       .main_clk       = "timer_sys_ck",
+       .main_clk       = "timer2_fck",
        .dev_attr       = &capability_alwon_dev_attr,
        .class          = &dm816x_timer_hwmod_class,
        .flags          = HWMOD_NO_IDLEST,
@@ -645,7 +645,7 @@ static struct omap_hwmod dm814x_timer2_hwmod = {
 static struct omap_hwmod_ocp_if dm814x_l4_ls__timer2 = {
        .master         = &dm81xx_l4_ls_hwmod,
        .slave          = &dm814x_timer2_hwmod,
-       .clk            = "timer_sys_ck",
+       .clk            = "timer2_fck",
        .user           = OCP_USER_MPU,
 };
 
@@ -1230,8 +1230,6 @@ static struct omap_hwmod_ocp_if dm81xx_tptc3__alwon_l3_fast = {
 
 /*
  * REVISIT: Test and enable the following once clocks work:
- * dm81xx_l4_ls__gpio1
- * dm81xx_l4_ls__gpio2
  * dm81xx_l4_ls__mailbox
  * dm81xx_alwon_l3_slow__gpmc
  * dm81xx_default_l3_slow__usbss
@@ -1250,6 +1248,8 @@ static struct omap_hwmod_ocp_if *dm814x_hwmod_ocp_ifs[] __initdata = {
        &dm81xx_l4_ls__wd_timer1,
        &dm81xx_l4_ls__i2c1,
        &dm81xx_l4_ls__i2c2,
+       &dm81xx_l4_ls__gpio1,
+       &dm81xx_l4_ls__gpio2,
        &dm81xx_l4_ls__elm,
        &dm81xx_l4_ls__mcspi1,
        &dm81xx_alwon_l3_fast__tpcc,
index 3fc2cbe52113b4c1b2f12a6f3cc4c33d874f4e30..5b2f5138d938ac626a1895b71a9a44cd0d757785 100644 (file)
@@ -664,6 +664,13 @@ static struct omap_prcm_init_data am3_prm_data __initdata = {
 };
 #endif
 
+#ifdef CONFIG_SOC_TI81XX
+static struct omap_prcm_init_data dm814_pllss_data __initdata = {
+       .index = TI_CLKM_PLLSS,
+       .init = am33xx_prm_init,
+};
+#endif
+
 #ifdef CONFIG_ARCH_OMAP4
 static struct omap_prcm_init_data omap4_prm_data __initdata = {
        .index = TI_CLKM_PRM,
@@ -715,6 +722,7 @@ static const struct of_device_id const omap_prcm_dt_match_table[] __initconst =
 #endif
 #ifdef CONFIG_SOC_TI81XX
        { .compatible = "ti,dm814-prcm", .data = &am3_prm_data },
+       { .compatible = "ti,dm814-pllss", .data = &dm814_pllss_data },
        { .compatible = "ti,dm816-prcm", .data = &am3_prm_data },
 #endif
 #ifdef CONFIG_ARCH_OMAP2
index 41e476e571d7f8b2be7a78b312fe3d699c8eebe8..d8965c682d2f74a800204dc55ecc6fae0d5def5f 100644 (file)
@@ -98,8 +98,8 @@ static void cs3_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 static int cs3_gpio_get(struct gpio_chip *chip, unsigned offset)
 {
        if (offset > 15)
-               return simpad_get_cs3_ro() & (1 << (offset - 16));
-       return simpad_get_cs3_shadow() & (1 << offset);
+               return !!(simpad_get_cs3_ro() & (1 << (offset - 16)));
+       return !!(simpad_get_cs3_shadow() & (1 << offset));
 };
 
 static int cs3_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
index e172920798ea0270bb681899a0af0e987660b615..9e85fcc74cc947399fcdaea76527737cab640cc6 100644 (file)
@@ -14,10 +14,14 @@ static struct ti_dt_clk dm814_clks[] = {
        DT_CLK(NULL, "devosc_ck", "devosc_ck"),
        DT_CLK(NULL, "mpu_ck", "mpu_ck"),
        DT_CLK(NULL, "sysclk4_ck", "sysclk4_ck"),
+       DT_CLK(NULL, "sysclk5_ck", "sysclk5_ck"),
        DT_CLK(NULL, "sysclk6_ck", "sysclk6_ck"),
+       DT_CLK(NULL, "sysclk8_ck", "sysclk8_ck"),
        DT_CLK(NULL, "sysclk10_ck", "sysclk10_ck"),
        DT_CLK(NULL, "sysclk18_ck", "sysclk18_ck"),
        DT_CLK(NULL, "timer_sys_ck", "devosc_ck"),
+       DT_CLK(NULL, "timer1_fck", "timer1_fck"),
+       DT_CLK(NULL, "timer2_fck", "timer2_fck"),
        DT_CLK(NULL, "cpsw_125mhz_gclk", "cpsw_125mhz_gclk"),
        DT_CLK(NULL, "cpsw_cpts_rft_clk", "cpsw_cpts_rft_clk"),
        { .node_name = NULL },
index 75205df29b9c7733776502c7365d08d5c037bb52..9a638601cb09f8918c8575e87893c397a64c7a54 100644 (file)
@@ -195,6 +195,7 @@ enum {
        TI_CLKM_PRM,
        TI_CLKM_SCRM,
        TI_CLKM_CTRL,
+       TI_CLKM_PLLSS,
        CLK_MAX_MEMMAPS
 };