drm/i915/psr: Add interface to notify PSR of vblank enable/disable
authorJouni Högander <jouni.hogander@intel.com>
Mon, 14 Apr 2025 10:05:04 +0000 (13:05 +0300)
committerJouni Högander <jouni.hogander@intel.com>
Wed, 23 Apr 2025 09:16:30 +0000 (12:16 +0300)
To implement Wa_16025596647 we need to get notification of vblank interrupt
enable/disable. Add new interface to PSR code for this notification.

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Link: https://lore.kernel.org/r/20250414100508.1208774-10-jouni.hogander@intel.com
drivers/gpu/drm/i915/display/intel_psr.c
drivers/gpu/drm/i915/display/intel_psr.h

index cc69a5b6463dc2b4668645244a0f851701cef5a8..5e9277ccfe84a45a7d2f4a48b725b78aa26a784d 100644 (file)
@@ -3797,6 +3797,46 @@ unlock:
        }
 }
 
+/**
+ * intel_psr_notify_vblank_enable_disable - Notify PSR about enable/disable of vblank
+ * @display: intel display struct
+ * @enable: enable/disable
+ *
+ * This is targeted for underrun on idle PSR HW bug (Wa_16025596647) to apply
+ * remove the workaround when vblank is getting enabled/disabled
+ */
+void intel_psr_notify_vblank_enable_disable(struct intel_display *display,
+                                           bool enable)
+{
+       struct intel_encoder *encoder;
+
+       for_each_intel_encoder_with_psr(display->drm, encoder) {
+               struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+
+               mutex_lock(&intel_dp->psr.lock);
+               if (intel_dp->psr.panel_replay_enabled) {
+                       mutex_unlock(&intel_dp->psr.lock);
+                       break;
+               }
+
+               if (intel_dp->psr.enabled)
+                       intel_psr_apply_underrun_on_idle_wa_locked(intel_dp);
+
+               mutex_unlock(&intel_dp->psr.lock);
+               return;
+       }
+
+       /*
+        * NOTE: intel_display_power_set_target_dc_state is used
+        * only by PSR * code for DC3CO handling. DC3CO target
+        * state is currently disabled in * PSR code. If DC3CO
+        * is taken into use we need take that into account here
+        * as well.
+        */
+       intel_display_power_set_target_dc_state(display, enable ? DC_STATE_DISABLE :
+                                               DC_STATE_EN_UPTO_DC6);
+}
+
 static void
 psr_source_status(struct intel_dp *intel_dp, struct seq_file *m)
 {
index bfe368239bc2718b2f03572fb98733a6e0caef4a..a914b7ee3756a2c838c867560a9e0b931e29bc0b 100644 (file)
@@ -64,6 +64,8 @@ void intel_psr_notify_pipe_change(struct intel_atomic_state *state,
                                  struct intel_crtc *crtc, bool enable);
 void intel_psr_notify_dc5_dc6(struct intel_display *display);
 void intel_psr_dc5_dc6_wa_init(struct intel_display *display);
+void intel_psr_notify_vblank_enable_disable(struct intel_display *display,
+                                           bool enable);
 bool intel_psr_link_ok(struct intel_dp *intel_dp);
 
 void intel_psr_lock(const struct intel_crtc_state *crtc_state);