drm/amdgpu/gfx12: clean up kcq reset code

Replace kcq queue reset with existing function amdgpu_mes_reset_legacy_queue.

Signed-off-by: Jesse Zhang <jesse.zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
index ad5c4a5c95576a31ebf1c422a0792327ca61e3bc..50dca041d5891002a4e5fd7f454545769f9f8f8f 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
@@ -5236,24 +5236,16 @@ static int gfx_v12_0_reset_kgq(struct amdgpu_ring *ring, unsigned int vmid)
 static int gfx_v12_0_reset_kcq(struct amdgpu_ring *ring, unsigned int vmid)
 {
        struct amdgpu_device *adev = ring->adev;
-       int r, i;
+       int r;
 
        if (amdgpu_sriov_vf(adev))
                return -EINVAL;
 
-       amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
-       mutex_lock(&adev->srbm_mutex);
-       soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
-       WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 0x2);
-       WREG32_SOC15(GC, 0, regSPI_COMPUTE_QUEUE_RESET, 0x1);
-       for (i = 0; i < adev->usec_timeout; i++) {
-               if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1))
-                       break;
-               udelay(1);
+       r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, true);
+       if (r) {
+               dev_err(adev->dev, "reset via MMIO failed %d\n", r);
+               return r;
        }
-       soc24_grbm_select(adev, 0, 0, 0, 0);
-       mutex_unlock(&adev->srbm_mutex);
-       amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
 
        r = amdgpu_bo_reserve(ring->mqd_obj, false);
        if (unlikely(r != 0)) {