Merge tag 'riscv-for-linus-6.10-mw1' of git://git.kernel.org/pub/scm/linux/kernel...

Pull RISC-V updates from Palmer Dabbelt:

 - Add byte/half-word compare-and-exchange, emulated via LR/SC loops

 - Support for Rust

 - Support for Zihintpause in hwprobe

 - Add PR_RISCV_SET_ICACHE_FLUSH_CTX prctl()

 - Support lockless lockrefs

* tag 'riscv-for-linus-6.10-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (42 commits)
  riscv: defconfig: Enable CONFIG_CLK_SOPHGO_CV1800
  riscv: select ARCH_HAS_FAST_MULTIPLIER
  riscv: mm: still create swiotlb buffer for kmalloc() bouncing if required
  riscv: Annotate pgtable_l{4,5}_enabled with __ro_after_init
  riscv: Remove redundant CONFIG_64BIT from pgtable_l{4,5}_enabled
  riscv: mm: Always use an ASID to flush mm contexts
  riscv: mm: Preserve global TLB entries when switching contexts
  riscv: mm: Make asid_bits a local variable
  riscv: mm: Use a fixed layout for the MM context ID
  riscv: mm: Introduce cntx2asid/cntx2version helper macros
  riscv: Avoid TLB flush loops when affected by SiFive CIP-1200
  riscv: Apply SiFive CIP-1200 workaround to single-ASID sfence.vma
  riscv: mm: Combine the SMP and UP TLB flush code
  riscv: Only send remote fences when some other CPU is online
  riscv: mm: Broadcast kernel TLB flushes only when needed
  riscv: Use IPIs for remote cache/TLB flushes by default
  riscv: Factor out page table TLB synchronization
  riscv: Flush the instruction cache during SMP bringup
  riscv: hwprobe: export Zihintpause ISA extension
  riscv: misaligned: remove CONFIG_RISCV_M_MODE specific code
  ...

diff --cc Documentation/rust/arch-support.rst
index c9137710633a37d6c88c46191dbfc7e4fc4d32c6,4d1495ded2aac7ce7af5b47f85ad3367f0d1c53e..b13e19d8474432cf8e13b672a086d7cb49b038f9
--- 1/Documentation/rust/arch-support.rst
--- 2/Documentation/rust/arch-support.rst
+++ b/Documentation/rust/arch-support.rst
@@@ -16,7 -16,8 +16,8 @@@ support corresponds to ``S`` values in 
  Architecture   Level of support  Constraints
  =============  ================  ==============================================
  ``arm64``      Maintained        Little Endian only.
 -``loongarch``  Maintained        -
 +``loongarch``  Maintained        \-
+ ``riscv``      Maintained        ``riscv64`` only.
  ``um``         Maintained        ``x86_64`` only.
  ``x86``        Maintained        ``x86_64`` only.
  =============  ================  ==============================================

diff --cc arch/riscv/Kconfig
Simple merge

diff --cc arch/riscv/Makefile
index 1e002d8003c56dee8f26a1fd5f0c2b38b9f73391,1a2dca1e6a967b03571c31efa4af46592543d6fa..c537764ee3c90c9e6ef47ddf3920fd6577621ad5
--- 1/arch/riscv/Makefile
--- 2/arch/riscv/Makefile
+++ b/arch/riscv/Makefile
@@@ -133,7 -140,15 +140,15 @@@ boot             := arch/riscv/boo
  ifeq ($(CONFIG_XIP_KERNEL),y)
  KBUILD_IMAGE := $(boot)/xipImage
  else
 -ifeq ($(CONFIG_RISCV_M_MODE)$(CONFIG_ARCH_CANAAN),yy)
++ifeq ($(CONFIG_RISCV_M_MODE)$(CONFIG_SOC_CANAAN_K210),yy)
+ KBUILD_IMAGE := $(boot)/loader.bin
+ else
+ ifeq ($(CONFIG_EFI_ZBOOT),)
  KBUILD_IMAGE  := $(boot)/Image.gz
+ else
+ KBUILD_IMAGE := $(boot)/vmlinuz.efi
+ endif
+ endif
  endif
  
  libs-y += arch/riscv/lib/
@@@ -151,19 -166,8 +166,8 @@@ endi
  endif
  
  vdso-install-y                        += arch/riscv/kernel/vdso/vdso.so.dbg
 -vdso-install-$(CONFIG_COMPAT) += arch/riscv/kernel/compat_vdso/compat_vdso.so.dbg:../compat_vdso/compat_vdso.so
 +vdso-install-$(CONFIG_COMPAT) += arch/riscv/kernel/compat_vdso/compat_vdso.so.dbg
  
- ifneq ($(CONFIG_XIP_KERNEL),y)
- ifeq ($(CONFIG_RISCV_M_MODE)$(CONFIG_SOC_CANAAN_K210),yy)
- KBUILD_IMAGE := $(boot)/loader.bin
- else
- ifeq ($(CONFIG_EFI_ZBOOT),)
- KBUILD_IMAGE := $(boot)/Image.gz
- else
- KBUILD_IMAGE := $(boot)/vmlinuz.efi
- endif
- endif
- endif
  BOOT_TARGETS := Image Image.gz loader loader.bin xipImage vmlinuz.efi
  
  all:  $(notdir $(KBUILD_IMAGE))

diff --cc arch/riscv/configs/defconfig
Simple merge

diff --cc arch/riscv/include/asm/errata_list.h
Simple merge

diff --cc arch/riscv/include/asm/sbi.h
Simple merge

diff --cc arch/riscv/include/uapi/asm/hwprobe.h
Simple merge

diff --cc arch/riscv/kernel/patch.c
Simple merge

diff --cc arch/riscv/mm/init.c
Simple merge

diff --cc arch/riscv/mm/tlbflush.c
Simple merge

diff --cc include/linux/cpumask.h
Simple merge

diff --cc include/uapi/linux/prctl.h
index 713d28788df7426754ea4cce5d0a30435f99e3c9,524d546d697b54ff273ef809cde7af6b486ba591..35791791a879b288f02fecb6803e5eaeec609fc4
--- 1/include/uapi/linux/prctl.h
--- 2/include/uapi/linux/prctl.h
+++ b/include/uapi/linux/prctl.h
@@@ -306,20 -306,10 +306,26 @@@ struct prctl_mm_map 
  # define PR_RISCV_V_VSTATE_CTRL_NEXT_MASK     0xc
  # define PR_RISCV_V_VSTATE_CTRL_MASK          0x1f
  
+ #define PR_RISCV_SET_ICACHE_FLUSH_CTX 71
+ # define PR_RISCV_CTX_SW_FENCEI_ON    0
+ # define PR_RISCV_CTX_SW_FENCEI_OFF   1
+ # define PR_RISCV_SCOPE_PER_PROCESS   0
+ # define PR_RISCV_SCOPE_PER_THREAD    1
+ 
 +/* PowerPC Dynamic Execution Control Register (DEXCR) controls */
 +#define PR_PPC_GET_DEXCR              72
 +#define PR_PPC_SET_DEXCR              73
 +/* DEXCR aspect to act on */
 +# define PR_PPC_DEXCR_SBHE            0 /* Speculative branch hint enable */
 +# define PR_PPC_DEXCR_IBRTPD          1 /* Indirect branch recurrent target prediction disable */
 +# define PR_PPC_DEXCR_SRAPD           2 /* Subroutine return address prediction disable */
 +# define PR_PPC_DEXCR_NPHIE           3 /* Non-privileged hash instruction enable */
 +/* Action to apply / return */
 +# define PR_PPC_DEXCR_CTRL_EDITABLE    0x1 /* Aspect can be modified with PR_PPC_SET_DEXCR */
 +# define PR_PPC_DEXCR_CTRL_SET                 0x2 /* Set the aspect for this process */
 +# define PR_PPC_DEXCR_CTRL_CLEAR       0x4 /* Clear the aspect for this process */
 +# define PR_PPC_DEXCR_CTRL_SET_ONEXEC  0x8 /* Set the aspect on exec */
 +# define PR_PPC_DEXCR_CTRL_CLEAR_ONEXEC       0x10 /* Clear the aspect on exec */
 +# define PR_PPC_DEXCR_CTRL_MASK               0x1f
 +
  #endif /* _LINUX_PRCTL_H */

diff --cc kernel/sys.c
index f9c95410278c46eb812b65170e67689795cf7412,1b7bda0722ca19f3fcbfcdc0e1c3301c752a494a..3a2df1bd9f640ebbd63ceda94dd8cc1c51018f1b
--- 1/kernel/sys.c
--- 2/kernel/sys.c
+++ b/kernel/sys.c
@@@ -146,12 -146,9 +146,15 @@@
  #ifndef RISCV_V_GET_CONTROL
  # define RISCV_V_GET_CONTROL()                (-EINVAL)
  #endif
+ #ifndef RISCV_SET_ICACHE_FLUSH_CTX
+ # define RISCV_SET_ICACHE_FLUSH_CTX(a, b)     (-EINVAL)
+ #endif
 +#ifndef PPC_GET_DEXCR_ASPECT
 +# define PPC_GET_DEXCR_ASPECT(a, b)   (-EINVAL)
 +#endif
 +#ifndef PPC_SET_DEXCR_ASPECT
 +# define PPC_SET_DEXCR_ASPECT(a, b, c)        (-EINVAL)
 +#endif
  
  /*
   * this is where the system-wide overflow UID and GID are defined, for

diff --cc scripts/generate_rust_target.rs
Simple merge