arm64: dts: imx8mq: disable DDRC node by default
authorLucas Stach <dev@lynxeye.de>
Sat, 18 Dec 2021 18:18:08 +0000 (19:18 +0100)
committerShawn Guo <shawnguo@kernel.org>
Fri, 11 Feb 2022 03:16:17 +0000 (11:16 +0800)
Without a OPP table or a downstream TF-A running on the system the DDRC will
fail to probe, as it has no means to scale the DRAM frequency in that case.
This however will block the bus scaling driver to come up and this in turn
prevents other devices that hook into the interconnect from probing.

If the DDRC is disabled, the interconnect driver will simply ignore it. As
most systems don't want to scale the DRAM frequency, disable the node by
default and only enable it on the systems that actually uses this
capability and provides a valid OPP table in the DT.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Acked-by: Martin Kepplinger <martin.kepplinger@puri.sm>
Reviewed-by: Guido Günther <agx@sigxcpu.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
arch/arm64/boot/dts/freescale/imx8mq-evk.dts
arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi
arch/arm64/boot/dts/freescale/imx8mq.dtsi

index a1b7582f3ecffa08eeffa4f02f0714305cca704c..e7f521aac400b012a347fbe8d09d6430d1838f8f 100644 (file)
 
 &ddrc {
        operating-points-v2 = <&ddrc_opp_table>;
+       status = "okay";
 
        ddrc_opp_table: opp-table {
                compatible = "operating-points-v2";
index f3e3418f7edc0ec270a5ff3f7c42a702534b7a0b..4429a0471bad38460309077ab3e1ce394b9024c6 100644 (file)
 
 &ddrc {
        operating-points-v2 = <&ddrc_opp_table>;
+       status = "okay";
 
        ddrc_opp_table: opp-table {
                compatible = "operating-points-v2";
index 2df2510d011841d4eecaae2de6a67bebc3765a1b..94d09dcf09b0ef733624f8e2ae8cb0650fcbf3f1 100644 (file)
                                 <&clk IMX8MQ_DRAM_PLL_OUT>,
                                 <&clk IMX8MQ_CLK_DRAM_ALT>,
                                 <&clk IMX8MQ_CLK_DRAM_APB>;
+                       status = "disabled";
                };
 
                ddr-pmu@3d800000 {