pinctrl: at91: Enable slewrate by default on SAM9X60

On SAM9X60, slewrate should be enabled on pins with a switching frequency
below 50Mhz. Since most of our pins do not exceed this value, we enable
slewrate by default. Pins with a switching value that exceeds 50Mhz will
have to explicitly disable slewrate.

This patch changes the ABI. However, the slewrate macros are only used
by SAM9X60 and, at this moment, there are no device-tree files available
for this platform.

Suggested-by: Ludovic Desroches <ludovic.desroches@microchip.com>
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>
Link: https://lore.kernel.org/r/20191101092031.24896-1-codrin.ciubotariu@microchip.com
Acked-by: Ludovic Desroches <ludovic.desroches@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
index 117075b5798fe593942cde1d9af26148a4514ee3..c135149e84e9954a74946276d484664954631d39 100644 (file)
--- a/drivers/pinctrl/pinctrl-at91.c
+++ b/drivers/pinctrl/pinctrl-at91.c
@@ -85,8 +85,8 @@ enum drive_strength_bit {
                                         DRIVE_STRENGTH_SHIFT)
 
 enum slewrate_bit {
-       SLEWRATE_BIT_DIS,
        SLEWRATE_BIT_ENA,
+       SLEWRATE_BIT_DIS,
 };
 
 #define SLEWRATE_BIT_MSK(name)         (SLEWRATE_BIT_##name << SLEWRATE_SHIFT)
@@ -669,7 +669,7 @@ static void at91_mux_sam9x60_set_slewrate(void __iomem *pio, unsigned pin,
 {
        unsigned int tmp;
 
-       if (setting < SLEWRATE_BIT_DIS || setting > SLEWRATE_BIT_ENA)
+       if (setting < SLEWRATE_BIT_ENA || setting > SLEWRATE_BIT_DIS)
                return;
 
        tmp = readl_relaxed(pio + SAM9X60_PIO_SLEWR);

diff --git a/include/dt-bindings/pinctrl/at91.h b/include/dt-bindings/pinctrl/at91.h
index 3831f91fb3ba374c21d402f0ec4c198aeb0d86e2..e8e117306b1bd4fa3ca86e86423aeb4aeb3bba92 100644 (file)
--- a/include/dt-bindings/pinctrl/at91.h
+++ b/include/dt-bindings/pinctrl/at91.h
@@ -27,8 +27,8 @@
 #define AT91_PINCTRL_DRIVE_STRENGTH_MED                        (0x2 << 5)
 #define AT91_PINCTRL_DRIVE_STRENGTH_HI                 (0x3 << 5)
 
-#define AT91_PINCTRL_SLEWRATE_DIS      (0x0 << 9)
-#define AT91_PINCTRL_SLEWRATE_ENA      (0x1 << 9)
+#define AT91_PINCTRL_SLEWRATE_ENA      (0x0 << 9)
+#define AT91_PINCTRL_SLEWRATE_DIS      (0x1 << 9)
 
 #define AT91_PIOA      0
 #define AT91_PIOB      1