[XTENSA] Fix icache flush for cache aliasing
authorChris Zankel <chris@zankel.net>
Tue, 12 Feb 2008 18:11:45 +0000 (10:11 -0800)
committerChris Zankel <chris@zankel.net>
Thu, 14 Feb 2008 01:08:18 +0000 (17:08 -0800)
Set the execution bit in the temporary TLB when we flush the
instruction cache.

Signed-off-by: Chris Zankel <chris@zankel.net>
arch/xtensa/mm/misc.S

index e1f880368e3276e5eaaaa395530e1f457ac0008c..c885664211d15ffea236ae0fc4fe32c61d7a1155 100644 (file)
@@ -295,7 +295,7 @@ ENTRY(__tlbtemp_mapping_itlb)
 ENTRY(__invalidate_icache_page_alias)
        entry   sp, 16
 
-       addi    a6, a3, (PAGE_KERNEL | _PAGE_HW_WRITE)
+       addi    a6, a3, (PAGE_KERNEL_EXEC | _PAGE_HW_WRITE)
        mov     a4, a2
        witlb   a6, a2
        isync