drm/nouveau/instmem: add hal for set_bar0_window_addr()
authorBen Skeggs <bskeggs@nvidia.com>
Thu, 30 Jan 2025 07:28:02 +0000 (17:28 +1000)
committerDave Airlie <airlied@redhat.com>
Sun, 18 May 2025 20:29:26 +0000 (06:29 +1000)
GH100/GBxxx have moved the register that controls where in VRAM the
the BAR0 NV_PRAMIN window points.

Add a HAL for this, as the BAR0 window is needed for BAR2 bootstrap.

Signed-off-by: Ben Skeggs <bskeggs@nvidia.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Timur Tabi <ttabi@nvidia.com>
Tested-by: Timur Tabi <ttabi@nvidia.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fbsr.c
drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c
drivers/gpu/drm/nouveau/nvkm/subdev/instmem/priv.h

index 1976d0030d177ba724aa0218a0a3955d1621c6eb..150e22fde2ac20ca1016b1d00b26669277fa7b17 100644 (file)
@@ -317,6 +317,7 @@ r535_instmem_new(const struct nvkm_instmem_func *hw,
        rm->memory_new = hw->memory_new;
        rm->memory_wrap = hw->memory_wrap;
        rm->zero = false;
+       rm->set_bar0_window_addr = hw->set_bar0_window_addr;
 
        ret = nv50_instmem_new_(rm, device, type, inst, pinstmem);
        if (ret)
index dd5b5a17ece0beed225888888d6c01a0afcf67c9..0ef66d7d5e511e7f7652d1180e8cc9c548c10e26 100644 (file)
@@ -65,7 +65,7 @@ nv50_instobj_wr32_slow(struct nvkm_memory *memory, u64 offset, u32 data)
 
        spin_lock_irqsave(&imem->base.lock, flags);
        if (unlikely(imem->addr != base)) {
-               nvkm_wr32(device, 0x001700, base >> 16);
+               imem->base.func->set_bar0_window_addr(device, base);
                imem->addr = base;
        }
        nvkm_wr32(device, 0x700000 + addr, data);
@@ -85,7 +85,7 @@ nv50_instobj_rd32_slow(struct nvkm_memory *memory, u64 offset)
 
        spin_lock_irqsave(&imem->base.lock, flags);
        if (unlikely(imem->addr != base)) {
-               nvkm_wr32(device, 0x001700, base >> 16);
+               imem->base.func->set_bar0_window_addr(device, base);
                imem->addr = base;
        }
        data = nvkm_rd32(device, 0x700000 + addr);
@@ -394,6 +394,12 @@ nv50_instobj_new(struct nvkm_instmem *imem, u32 size, u32 align, bool zero,
  * instmem subdev implementation
  *****************************************************************************/
 
+static void
+nv50_instmem_set_bar0_window_addr(struct nvkm_device *device, u64 addr)
+{
+       nvkm_wr32(device, 0x001700, addr >> 16);
+}
+
 static void
 nv50_instmem_fini(struct nvkm_instmem *base)
 {
@@ -415,6 +421,7 @@ nv50_instmem = {
        .memory_new = nv50_instobj_new,
        .memory_wrap = nv50_instobj_wrap,
        .zero = false,
+       .set_bar0_window_addr = nv50_instmem_set_bar0_window_addr,
 };
 
 int
index 4c14c96fb60a28cdf940784809c4050bda3dc24d..d5b5fcd9262b1d199b9b3b62798432e39ef268af 100644 (file)
@@ -16,6 +16,7 @@ struct nvkm_instmem_func {
                          bool zero, struct nvkm_memory **);
        int (*memory_wrap)(struct nvkm_instmem *, struct nvkm_memory *, struct nvkm_memory **);
        bool zero;
+       void (*set_bar0_window_addr)(struct nvkm_device *, u64 addr);
 };
 
 int nv50_instmem_new_(const struct nvkm_instmem_func *, struct nvkm_device *,