drm/msm/dpu: move dpu_encoder_helper_phys_setup_cdm to dpu_encoder

Move dpu_encoder_helper_phys_setup_cdm to dpu_encoder in preparation for
implementing YUV420 over DP, which requires CDM compatibility.

Changes in v2:
	- Slightly change the wording of the commit text to make clear
	  that YUV over DP requires CDM

Signed-off-by: Paloma Arellano <quic_parellan@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/579611/
Link: https://lore.kernel.org/r/20240222194025.25329-6-quic_parellan@quicinc.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 194dbb08331d23b8f8a511d0e6376e3a8ffe7708..c55178b5f5eedfabc58ec9ec975a2672281e439e 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -2133,6 +2133,84 @@ void dpu_encoder_helper_phys_cleanup(struct dpu_encoder_phys *phys_enc)
        ctl->ops.clear_pending_flush(ctl);
 }
 
+void dpu_encoder_helper_phys_setup_cdm(struct dpu_encoder_phys *phys_enc,
+                                      const struct dpu_format *dpu_fmt,
+                                      u32 output_type)
+{
+       struct dpu_hw_cdm *hw_cdm;
+       struct dpu_hw_cdm_cfg *cdm_cfg;
+       struct dpu_hw_pingpong *hw_pp;
+       int ret;
+
+       if (!phys_enc)
+               return;
+
+       cdm_cfg = &phys_enc->cdm_cfg;
+       hw_pp = phys_enc->hw_pp;
+       hw_cdm = phys_enc->hw_cdm;
+
+       if (!hw_cdm)
+               return;
+
+       if (!DPU_FORMAT_IS_YUV(dpu_fmt)) {
+               DPU_DEBUG("[enc:%d] cdm_disable fmt:%x\n", DRMID(phys_enc->parent),
+                         dpu_fmt->base.pixel_format);
+               if (hw_cdm->ops.bind_pingpong_blk)
+                       hw_cdm->ops.bind_pingpong_blk(hw_cdm, PINGPONG_NONE);
+
+               return;
+       }
+
+       memset(cdm_cfg, 0, sizeof(struct dpu_hw_cdm_cfg));
+
+       cdm_cfg->output_width = phys_enc->cached_mode.hdisplay;
+       cdm_cfg->output_height = phys_enc->cached_mode.vdisplay;
+       cdm_cfg->output_fmt = dpu_fmt;
+       cdm_cfg->output_type = output_type;
+       cdm_cfg->output_bit_depth = DPU_FORMAT_IS_DX(dpu_fmt) ?
+                       CDM_CDWN_OUTPUT_10BIT : CDM_CDWN_OUTPUT_8BIT;
+       cdm_cfg->csc_cfg = &dpu_csc10_rgb2yuv_601l;
+
+       /* enable 10 bit logic */
+       switch (cdm_cfg->output_fmt->chroma_sample) {
+       case DPU_CHROMA_RGB:
+               cdm_cfg->h_cdwn_type = CDM_CDWN_DISABLE;
+               cdm_cfg->v_cdwn_type = CDM_CDWN_DISABLE;
+               break;
+       case DPU_CHROMA_H2V1:
+               cdm_cfg->h_cdwn_type = CDM_CDWN_COSITE;
+               cdm_cfg->v_cdwn_type = CDM_CDWN_DISABLE;
+               break;
+       case DPU_CHROMA_420:
+               cdm_cfg->h_cdwn_type = CDM_CDWN_COSITE;
+               cdm_cfg->v_cdwn_type = CDM_CDWN_OFFSITE;
+               break;
+       case DPU_CHROMA_H1V2:
+       default:
+               DPU_ERROR("[enc:%d] unsupported chroma sampling type\n",
+                         DRMID(phys_enc->parent));
+               cdm_cfg->h_cdwn_type = CDM_CDWN_DISABLE;
+               cdm_cfg->v_cdwn_type = CDM_CDWN_DISABLE;
+               break;
+       }
+
+       DPU_DEBUG("[enc:%d] cdm_enable:%d,%d,%X,%d,%d,%d,%d]\n",
+                 DRMID(phys_enc->parent), cdm_cfg->output_width,
+                 cdm_cfg->output_height, cdm_cfg->output_fmt->base.pixel_format,
+                 cdm_cfg->output_type, cdm_cfg->output_bit_depth,
+                 cdm_cfg->h_cdwn_type, cdm_cfg->v_cdwn_type);
+
+       if (hw_cdm->ops.enable) {
+               cdm_cfg->pp_id = hw_pp->idx;
+               ret = hw_cdm->ops.enable(hw_cdm, cdm_cfg);
+               if (ret < 0) {
+                       DPU_ERROR("[enc:%d] failed to enable CDM; ret:%d\n",
+                                 DRMID(phys_enc->parent), ret);
+                       return;
+               }
+       }
+}
+
 #ifdef CONFIG_DEBUG_FS
 static int _dpu_encoder_status_show(struct seq_file *s, void *data)
 {

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
index b6c005d932eb43cef55f666c261d525f7a473251..cb10869790aacfe979c41a71023b49b3e8c930c1 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
@@ -374,6 +374,15 @@ int dpu_encoder_helper_wait_for_irq(struct dpu_encoder_phys *phys_enc,
  */
 void dpu_encoder_helper_phys_cleanup(struct dpu_encoder_phys *phys_enc);
 
+/**
+ * dpu_encoder_helper_phys_setup_cdm - setup chroma down sampling block
+ * @phys_enc: Pointer to physical encoder
+ * @output_type: HDMI/WB
+ */
+void dpu_encoder_helper_phys_setup_cdm(struct dpu_encoder_phys *phys_enc,
+                                      const struct dpu_format *dpu_fmt,
+                                      u32 output_type);
+
 /**
  * dpu_encoder_vblank_callback - Notify virtual encoder of vblank IRQ reception
  * @drm_enc:    Pointer to drm encoder structure

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
index 208b7c84e802887237fdd7cf596def7212e228d0..1924a2b28e53c5932570a15a13e370a750a177cb 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
@@ -264,89 +264,6 @@ static void dpu_encoder_phys_wb_setup_ctl(struct dpu_encoder_phys *phys_enc)
        }
 }
 
-/**
- * dpu_encoder_helper_phys_setup_cdm - setup chroma down sampling block
- *                                     This API does not handle DPU_CHROMA_H1V2.
- * @phys_enc:Pointer to physical encoder
- */
-static void dpu_encoder_helper_phys_setup_cdm(struct dpu_encoder_phys *phys_enc,
-                                             const struct dpu_format *dpu_fmt,
-                                             u32 output_type)
-{
-       struct dpu_hw_cdm *hw_cdm;
-       struct dpu_hw_cdm_cfg *cdm_cfg;
-       struct dpu_hw_pingpong *hw_pp;
-       int ret;
-
-       if (!phys_enc)
-               return;
-
-       cdm_cfg = &phys_enc->cdm_cfg;
-       hw_pp = phys_enc->hw_pp;
-       hw_cdm = phys_enc->hw_cdm;
-
-       if (!hw_cdm)
-               return;
-
-       if (!DPU_FORMAT_IS_YUV(dpu_fmt)) {
-               DPU_DEBUG("[enc:%d] cdm_disable fmt:%x\n", DRMID(phys_enc->parent),
-                         dpu_fmt->base.pixel_format);
-               if (hw_cdm->ops.bind_pingpong_blk)
-                       hw_cdm->ops.bind_pingpong_blk(hw_cdm, PINGPONG_NONE);
-
-               return;
-       }
-
-       memset(cdm_cfg, 0, sizeof(struct dpu_hw_cdm_cfg));
-
-       cdm_cfg->output_width = phys_enc->cached_mode.hdisplay;
-       cdm_cfg->output_height = phys_enc->cached_mode.vdisplay;
-       cdm_cfg->output_fmt = dpu_fmt;
-       cdm_cfg->output_type = output_type;
-       cdm_cfg->output_bit_depth = DPU_FORMAT_IS_DX(dpu_fmt) ?
-                       CDM_CDWN_OUTPUT_10BIT : CDM_CDWN_OUTPUT_8BIT;
-       cdm_cfg->csc_cfg = &dpu_csc10_rgb2yuv_601l;
-
-       /* enable 10 bit logic */
-       switch (cdm_cfg->output_fmt->chroma_sample) {
-       case DPU_CHROMA_RGB:
-               cdm_cfg->h_cdwn_type = CDM_CDWN_DISABLE;
-               cdm_cfg->v_cdwn_type = CDM_CDWN_DISABLE;
-               break;
-       case DPU_CHROMA_H2V1:
-               cdm_cfg->h_cdwn_type = CDM_CDWN_COSITE;
-               cdm_cfg->v_cdwn_type = CDM_CDWN_DISABLE;
-               break;
-       case DPU_CHROMA_420:
-               cdm_cfg->h_cdwn_type = CDM_CDWN_COSITE;
-               cdm_cfg->v_cdwn_type = CDM_CDWN_OFFSITE;
-               break;
-       case DPU_CHROMA_H1V2:
-       default:
-               DPU_ERROR("[enc:%d] unsupported chroma sampling type\n",
-                         DRMID(phys_enc->parent));
-               cdm_cfg->h_cdwn_type = CDM_CDWN_DISABLE;
-               cdm_cfg->v_cdwn_type = CDM_CDWN_DISABLE;
-               break;
-       }
-
-       DPU_DEBUG("[enc:%d] cdm_enable:%d,%d,%X,%d,%d,%d,%d]\n",
-                 DRMID(phys_enc->parent), cdm_cfg->output_width,
-                 cdm_cfg->output_height, cdm_cfg->output_fmt->base.pixel_format,
-                 cdm_cfg->output_type, cdm_cfg->output_bit_depth,
-                 cdm_cfg->h_cdwn_type, cdm_cfg->v_cdwn_type);
-
-       if (hw_cdm->ops.enable) {
-               cdm_cfg->pp_id = hw_pp->idx;
-               ret = hw_cdm->ops.enable(hw_cdm, cdm_cfg);
-               if (ret < 0) {
-                       DPU_ERROR("[enc:%d] failed to enable CDM; ret:%d\n",
-                                 DRMID(phys_enc->parent), ret);
-                       return;
-               }
-       }
-}
-
 /**
  * _dpu_encoder_phys_wb_update_flush - flush hardware update
  * @phys_enc:  Pointer to physical encoder