Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux

Pull more arm64 fixes from Will Deacon:

 - Fix incorrect LDADD instruction encoding in our disassembly macros

 - Disable the broken ARM64_PSEUDO_NMI support for now

 - Add workaround for Cortex-A76 CPU erratum #1463225

 - Handle Cortex-A76/Neoverse-N1 erratum #1418040 w/ existing workaround

 - Fix IORT build failure if IOMMU_SUPPORT=n

 - Fix place-relative module relocation range checking and its
   interaction with KASLR

* tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux:
  arm64: insn: Add BUILD_BUG_ON() for invalid masks
  arm64: insn: Fix ldadd instruction encoding
  arm64: Kconfig: Make ARM64_PSEUDO_NMI depend on BROKEN for now
  arm64: Handle erratum 1418040 as a superset of erratum 1188873
  arm64/module: deal with ambiguity in PRELxx relocation ranges
  ACPI/IORT: Fix build error when IOMMU_SUPPORT is disabled
  arm64/kernel: kaslr: reduce module randomization range to 2 GB
  arm64: errata: Add workaround for Cortex-A76 erratum #1463225
  arm64: Remove useless message during oops

diff --combined arch/arm64/Kconfig
index ca9c175fb9498a2ea14a814e4a9d567c2c4ad765,f6275c265d41642d05d34f9f966e18de01b50ebd..697ea05107298bf145453f267f6bb4d1c385a10d
--- 1/arch/arm64/Kconfig
--- 2/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@@ -1,4 -1,3 +1,4 @@@
 +# SPDX-License-Identifier: GPL-2.0-only
  config ARM64
        def_bool y
        select ACPI_CCA_REQUIRED if ACPI
@@@ -69,7 -68,7 +69,7 @@@
        select ARCH_SUPPORTS_ATOMIC_RMW
        select ARCH_SUPPORTS_INT128 if GCC_VERSION >= 50000 || CC_IS_CLANG
        select ARCH_SUPPORTS_NUMA_BALANCING
 -      select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
 +      select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT
        select ARCH_WANT_FRAME_POINTERS
        select ARCH_HAS_UBSAN_SANITIZE_ALL
        select ARM_AMBA
@@@ -476,16 -475,15 +476,15 @@@ config ARM64_ERRATUM_102471
  
          If unsure, say Y.
  
- config ARM64_ERRATUM_1188873
+ config ARM64_ERRATUM_1418040
        bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
        default y
        depends on COMPAT
-       select ARM_ARCH_TIMER_OOL_WORKAROUND
        help
          This option adds a workaround for ARM Cortex-A76/Neoverse-N1
-         erratum 1188873.
+         errata 1188873 and 1418040.
  
-         Affected Cortex-A76/Neoverse-N1 cores (r0p0, r1p0, r2p0) could
+         Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
          cause register corruption when accessing the timer registers
          from AArch32 userspace.
  
@@@ -521,6 -519,24 +520,24 @@@ config ARM64_ERRATUM_128680
  
          If unsure, say Y.
  
+ config ARM64_ERRATUM_1463225
+       bool "Cortex-A76: Software Step might prevent interrupt recognition"
+       default y
+       help
+         This option adds a workaround for Arm Cortex-A76 erratum 1463225.
+ 
+         On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
+         of a system call instruction (SVC) can prevent recognition of
+         subsequent interrupts when software stepping is disabled in the
+         exception handler of the system call and either kernel debugging
+         is enabled or VHE is in use.
+ 
+         Work around the erratum by triggering a dummy step exception
+         when handling a system call from a task that is being stepped
+         in a VHE configuration of the kernel.
+ 
+         If unsure, say Y.
+ 
  config CAVIUM_ERRATUM_22375
        bool "Cavium erratum 22375, 24313"
        default y
@@@ -1406,6 -1422,7 +1423,7 @@@ config ARM64_MODULE_PLT
  
  config ARM64_PSEUDO_NMI
        bool "Support for NMI-like interrupts"
+       depends on BROKEN # 1556553607-46531-1-git-send-email-julien.thierry@arm.com
        select CONFIG_ARM_GIC_V3
        help
          Adds support for mimicking Non-Maskable Interrupts through the use of

diff --combined arch/arm64/mm/fault.c
index dda234bcc020cd109a8594f2898a16a38c5dc616,9a84a407156106976465c5e08c74569eecaa6296..a30818ed9c607422b576945d6976b0c0ed949887
--- 1/arch/arm64/mm/fault.c
--- 2/arch/arm64/mm/fault.c
+++ b/arch/arm64/mm/fault.c
@@@ -171,10 -171,9 +171,10 @@@ static void show_pte(unsigned long addr
                return;
        }
  
 -      pr_alert("%s pgtable: %luk pages, %u-bit VAs, pgdp = %p\n",
 +      pr_alert("%s pgtable: %luk pages, %u-bit VAs, pgdp=%016lx\n",
                 mm == &init_mm ? "swapper" : "user", PAGE_SIZE / SZ_1K,
 -               mm == &init_mm ? VA_BITS : (int) vabits_user, mm->pgd);
 +               mm == &init_mm ? VA_BITS : (int)vabits_user,
 +               (unsigned long)virt_to_phys(mm->pgd));
        pgdp = pgd_offset(mm, addr);
        pgd = READ_ONCE(*pgdp);
        pr_alert("[%016lx] pgd=%016llx", addr, pgd_val(pgd));
@@@ -811,6 -810,36 +811,36 @@@ void __init hook_debug_fault_code(int n
        debug_fault_info[nr].name       = name;
  }
  
+ #ifdef CONFIG_ARM64_ERRATUM_1463225
+ DECLARE_PER_CPU(int, __in_cortex_a76_erratum_1463225_wa);
+ 
+ static int __exception
+ cortex_a76_erratum_1463225_debug_handler(struct pt_regs *regs)
+ {
+       if (user_mode(regs))
+               return 0;
+ 
+       if (!__this_cpu_read(__in_cortex_a76_erratum_1463225_wa))
+               return 0;
+ 
+       /*
+        * We've taken a dummy step exception from the kernel to ensure
+        * that interrupts are re-enabled on the syscall path. Return back
+        * to cortex_a76_erratum_1463225_svc_handler() with debug exceptions
+        * masked so that we can safely restore the mdscr and get on with
+        * handling the syscall.
+        */
+       regs->pstate |= PSR_D_BIT;
+       return 1;
+ }
+ #else
+ static int __exception
+ cortex_a76_erratum_1463225_debug_handler(struct pt_regs *regs)
+ {
+       return 0;
+ }
+ #endif /* CONFIG_ARM64_ERRATUM_1463225 */
+ 
  asmlinkage void __exception do_debug_exception(unsigned long addr_if_watchpoint,
                                               unsigned int esr,
                                               struct pt_regs *regs)
@@@ -818,6 -847,9 +848,9 @@@
        const struct fault_info *inf = esr_to_debug_fault_info(esr);
        unsigned long pc = instruction_pointer(regs);
  
+       if (cortex_a76_erratum_1463225_debug_handler(regs))
+               return;
+ 
        /*
         * Tell lockdep we disabled irqs in entry.S. Do nothing if they were
         * already disabled to preserve the last enabled/disabled addresses.