drm/i915: Simplify the link training functions

Split the prepare, link training, fallback-handling steps into their own
functions for clarity and as a preparation for the upcoming LTTPR
changes.

While at it also:
- Unexport and inline intel_dp_set_idle_link_train(), which is used at a
  single place.
- Add some documentation to functions that are exported or that can use
  a better description about which part of the LT sequence they
  implement.

v2: (Ville)
- Unexport/inline intel_dp_set_idle_link_train()
- Make the documentation of
  intel_dp_prepare_link_train()/intel_dp_stop_link_train() more accurate
  wrt. HW specific details.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20201007170917.1764556-3-imre.deak@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 53150b0392cf2d1eba93449771ccdc8d69795229..5a0a50d36dfb251f2f12c6d837852603f69517a2 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4572,13 +4572,6 @@ intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
        intel_dp->set_link_train(intel_dp, crtc_state, dp_train_pat);
 }
 
-void intel_dp_set_idle_link_train(struct intel_dp *intel_dp,
-                                 const struct intel_crtc_state *crtc_state)
-{
-       if (intel_dp->set_idle_link_train)
-               intel_dp->set_idle_link_train(intel_dp, crtc_state);
-}
-
 static void
 intel_dp_link_down(struct intel_encoder *encoder,
                   const struct intel_crtc_state *old_crtc_state)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 426d4968e15c75e1e30a04e7d104c93ed62b752a..7e2e711a7e1a1ccb212b4d10301d3ec5e9391cbb 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -98,8 +98,6 @@ intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
 void
 intel_dp_set_signal_levels(struct intel_dp *intel_dp,
                           const struct intel_crtc_state *crtc_state);
-void intel_dp_set_idle_link_train(struct intel_dp *intel_dp,
-                                 const struct intel_crtc_state *crtc_state);
 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
                           u8 *link_bw, u8 *rate_select);
 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);

diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index b2ff88a152cd9d15c36b92a89d7cd792e7373391..51d1316c37d5e474fa8c475447fb5986ca812c71 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -153,15 +153,15 @@ static bool intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp,
        return true;
 }
 
-/* Enable corresponding port and start training pattern 1 */
+/*
+ * Prepare link training by configuring the link parameters. On DDI platforms
+ * also enable the port here.
+ */
 static bool
-intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp,
-                                     const struct intel_crtc_state *crtc_state)
+intel_dp_prepare_link_train(struct intel_dp *intel_dp,
+                           const struct intel_crtc_state *crtc_state)
 {
        struct drm_i915_private *i915 = dp_to_i915(intel_dp);
-       u8 voltage;
-       int voltage_tries, cr_tries, max_cr_tries;
-       bool max_vswing_reached = false;
        u8 link_config[2];
        u8 link_bw, rate_select;
 
@@ -196,6 +196,19 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp,
 
        intel_dp->DP |= DP_PORT_EN;
 
+       return true;
+}
+
+/* Perform the link training clock recovery phase using training pattern 1. */
+static bool
+intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp,
+                                     const struct intel_crtc_state *crtc_state)
+{
+       struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+       u8 voltage;
+       int voltage_tries, cr_tries, max_cr_tries;
+       bool max_vswing_reached = false;
+
        /* clock recovery */
        if (!intel_dp_reset_link_train(intel_dp, crtc_state,
                                       DP_TRAINING_PATTERN_1 |
@@ -318,6 +331,10 @@ static u32 intel_dp_training_pattern(struct intel_dp *intel_dp,
        return DP_TRAINING_PATTERN_2;
 }
 
+/*
+ * Perform the link training channel equalization phase using one of training
+ * pattern 2, 3 or 4 depending on the source and sink capabilities.
+ */
 static bool
 intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp,
                                            const struct intel_crtc_state *crtc_state)
@@ -383,12 +400,28 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp,
                            "Channel equalization failed 5 times\n");
        }
 
-       intel_dp_set_idle_link_train(intel_dp, crtc_state);
+       if (intel_dp->set_idle_link_train)
+               intel_dp->set_idle_link_train(intel_dp, crtc_state);
 
        return channel_eq;
-
 }
 
+/**
+ * intel_dp_stop_link_train - stop link training
+ * @intel_dp: DP struct
+ * @crtc_state: state for CRTC attached to the encoder
+ *
+ * Stop the link training of the @intel_dp port, disabling the test pattern
+ * symbol generation on the port and disabling the training pattern in
+ * the sink's DPCD.
+ *
+ * What symbols are output on the port after this point is
+ * platform specific: On DDI/VLV/CHV platforms it will be the idle pattern
+ * with the pipe being disabled, on older platforms it's HW specific if/how an
+ * idle pattern is generated, as the pipe is already enabled here for those.
+ *
+ * This function must be called after intel_dp_start_link_train().
+ */
 void intel_dp_stop_link_train(struct intel_dp *intel_dp,
                              const struct intel_crtc_state *crtc_state)
 {
@@ -398,31 +431,39 @@ void intel_dp_stop_link_train(struct intel_dp *intel_dp,
                                DP_TRAINING_PATTERN_DISABLE);
 }
 
-void
-intel_dp_start_link_train(struct intel_dp *intel_dp,
-                         const struct intel_crtc_state *crtc_state)
+static bool
+intel_dp_link_train(struct intel_dp *intel_dp,
+                   const struct intel_crtc_state *crtc_state)
 {
        struct intel_connector *intel_connector = intel_dp->attached_connector;
+       bool ret = false;
+
+       intel_dp_prepare_link_train(intel_dp, crtc_state);
 
        if (!intel_dp_link_training_clock_recovery(intel_dp, crtc_state))
-               goto failure_handling;
+               goto out;
+
        if (!intel_dp_link_training_channel_equalization(intel_dp, crtc_state))
-               goto failure_handling;
+               goto out;
 
-       drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
-                   "[CONNECTOR:%d:%s] Link Training Passed at Link Rate = %d, Lane count = %d",
-                   intel_connector->base.base.id,
-                   intel_connector->base.name,
-                   crtc_state->port_clock, crtc_state->lane_count);
-       return;
+       ret = true;
 
- failure_handling:
+out:
        drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
-                   "[CONNECTOR:%d:%s] Link Training failed at link rate = %d, lane count = %d",
+                   "[CONNECTOR:%d:%s] Link Training %s at link rate = %d, lane count = %d",
                    intel_connector->base.base.id,
                    intel_connector->base.name,
+                   ret ? "passed" : "failed",
                    crtc_state->port_clock, crtc_state->lane_count);
 
+       return ret;
+}
+
+static void intel_dp_schedule_fallback_link_training(struct intel_dp *intel_dp,
+                                                    const struct intel_crtc_state *crtc_state)
+{
+       struct intel_connector *intel_connector = intel_dp->attached_connector;
+
        if (intel_dp->hobl_active) {
                drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
                            "Link Training failed with HOBL active, not enabling it from now on");
@@ -436,3 +477,20 @@ intel_dp_start_link_train(struct intel_dp *intel_dp,
        /* Schedule a Hotplug Uevent to userspace to start modeset */
        schedule_work(&intel_connector->modeset_retry_work);
 }
+
+/**
+ * intel_dp_start_link_train - start link training
+ * @intel_dp: DP struct
+ * @crtc_state: state for CRTC attached to the encoder
+ *
+ * Start the link training of the @intel_dp port, scheduling a fallback
+ * retraining with reduced link rate/lane parameters if the link training
+ * fails.
+ * After calling this function intel_dp_stop_link_train() must be called.
+ */
+void intel_dp_start_link_train(struct intel_dp *intel_dp,
+                              const struct intel_crtc_state *crtc_state)
+{
+       if (!intel_dp_link_train(intel_dp, crtc_state))
+               intel_dp_schedule_fallback_link_training(intel_dp, crtc_state);
+}