drm/amdgpu: split ip hw_init into 2 phases
authorRex Zhu <Rex.Zhu@amd.com>
Wed, 10 Oct 2018 11:28:30 +0000 (19:28 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 10 Oct 2018 19:49:09 +0000 (14:49 -0500)
We need to do some IPs earlier to deal with ordering issues
similar to how resume is split into two phases.

Will do fw loading via smu/psp between the two phases.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

index 680df0504f8601737a3040851db2eb6570dd87bc..372574abc1c4a31f614bdff9d42eee61eee00b41 100644 (file)
@@ -1525,6 +1525,51 @@ static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)
        return 0;
 }
 
+static int amdgpu_device_ip_hw_init_phase1(struct amdgpu_device *adev)
+{
+       int i, r;
+
+       for (i = 0; i < adev->num_ip_blocks; i++) {
+               if (!adev->ip_blocks[i].status.sw)
+                       continue;
+               if (adev->ip_blocks[i].status.hw)
+                       continue;
+               if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
+                   adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) {
+                       r = adev->ip_blocks[i].version->funcs->hw_init(adev);
+                       if (r) {
+                               DRM_ERROR("hw_init of IP block <%s> failed %d\n",
+                                         adev->ip_blocks[i].version->funcs->name, r);
+                               return r;
+                       }
+                       adev->ip_blocks[i].status.hw = true;
+               }
+       }
+
+       return 0;
+}
+
+static int amdgpu_device_ip_hw_init_phase2(struct amdgpu_device *adev)
+{
+       int i, r;
+
+       for (i = 0; i < adev->num_ip_blocks; i++) {
+               if (!adev->ip_blocks[i].status.sw)
+                       continue;
+               if (adev->ip_blocks[i].status.hw)
+                       continue;
+               r = adev->ip_blocks[i].version->funcs->hw_init(adev);
+               if (r) {
+                       DRM_ERROR("hw_init of IP block <%s> failed %d\n",
+                                 adev->ip_blocks[i].version->funcs->name, r);
+                       return r;
+               }
+               adev->ip_blocks[i].status.hw = true;
+       }
+
+       return 0;
+}
+
 /**
  * amdgpu_device_ip_init - run init for hardware IPs
  *
@@ -1584,19 +1629,14 @@ static int amdgpu_device_ip_init(struct amdgpu_device *adev)
        r = amdgpu_ucode_create_bo(adev); /* create ucode bo when sw_init complete*/
        if (r)
                return r;
-       for (i = 0; i < adev->num_ip_blocks; i++) {
-               if (!adev->ip_blocks[i].status.sw)
-                       continue;
-               if (adev->ip_blocks[i].status.hw)
-                       continue;
-               r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
-               if (r) {
-                       DRM_ERROR("hw_init of IP block <%s> failed %d\n",
-                                 adev->ip_blocks[i].version->funcs->name, r);
-                       return r;
-               }
-               adev->ip_blocks[i].status.hw = true;
-       }
+
+       r = amdgpu_device_ip_hw_init_phase1(adev);
+       if (r)
+               return r;
+
+       r = amdgpu_device_ip_hw_init_phase2(adev);
+       if (r)
+               return r;
 
        amdgpu_xgmi_add_device(adev);
        amdgpu_amdkfd_device_init(adev);